Analog multiplexer configured to reduce kickback perturbation in image sensor readout
First Claim
1. An analog multiplexer for multiplexing a plurality of input analog signal channels into a single output analog signal channel, the multiplexer comprising:
- a plurality of input sampling circuits associated with respective ones of the input analog signal channels, the input sampling circuits each comprising positive and negative inputs coupled to respective positive and negative differential signal lines of a corresponding input analog signal channel; and
a differential amplifier having positive and negative inputs controllably connectable in turn to each of the input sampling circuits;
wherein the analog multiplexer is further configured to connect the positive and negative inputs of a given input sampling circuit to respective first plates of respective first and second sampling capacitors at a predetermined time prior to connecting respective second plates of the first and second sampling capacitors to the respective positive and negative inputs of the differential amplifier;
wherein the predetermined time is less than a full clock cycle of a sampling clock of the amplifier; and
wherein the given input sampling circuit comprises;
a positive signal path having a first switch coupled between the positive input of the input sampling circuit and a first plate of a first sampling capacitor;
a negative signal path having a second switch coupled between the negative input of the input sampling circuit and a first plate of a second sampling capacitor;
third and fourth switches coupled between respective second plates of the first and second sampling capacitors and a common mode voltage reference; and
fifth and sixth switches arranged in series with the respective first and second switches and the respective first and second sampling capacitors in the respective positive and negative signal paths and coupled between the respective second plates of the first and second sampling capacitors and the respective positive and negative inputs of the differential amplifier.
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Abstract
An analog multiplexer is configured to multiplex a plurality of input analog signal channels into a single output analog signal channel. The analog multiplexer comprises a plurality of input sampling circuits associated with respective ones of the input analog signal channels and an amplifier having an input controllably connectable in turn to each of the input sampling circuits. The analog multiplexer is further configured to connect at least a given one of the input analog signal channels to a sampling element of its corresponding input sampling circuit at a predetermined time prior to connecting the sampling element of that input sampling circuit to the input of the amplifier. The predetermined time is less than a full clock cycle of a sampling clock of the amplifier. The analog multiplexer may be implemented in readout circuitry coupled to a pixel array in an image sensor.
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Citations
17 Claims
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1. An analog multiplexer for multiplexing a plurality of input analog signal channels into a single output analog signal channel, the multiplexer comprising:
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a plurality of input sampling circuits associated with respective ones of the input analog signal channels, the input sampling circuits each comprising positive and negative inputs coupled to respective positive and negative differential signal lines of a corresponding input analog signal channel; and a differential amplifier having positive and negative inputs controllably connectable in turn to each of the input sampling circuits; wherein the analog multiplexer is further configured to connect the positive and negative inputs of a given input sampling circuit to respective first plates of respective first and second sampling capacitors at a predetermined time prior to connecting respective second plates of the first and second sampling capacitors to the respective positive and negative inputs of the differential amplifier; wherein the predetermined time is less than a full clock cycle of a sampling clock of the amplifier; and wherein the given input sampling circuit comprises; a positive signal path having a first switch coupled between the positive input of the input sampling circuit and a first plate of a first sampling capacitor; a negative signal path having a second switch coupled between the negative input of the input sampling circuit and a first plate of a second sampling capacitor; third and fourth switches coupled between respective second plates of the first and second sampling capacitors and a common mode voltage reference; and fifth and sixth switches arranged in series with the respective first and second switches and the respective first and second sampling capacitors in the respective positive and negative signal paths and coupled between the respective second plates of the first and second sampling capacitors and the respective positive and negative inputs of the differential amplifier. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. An analog multiplexing method comprising the steps of:
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receiving a plurality of input analog signal channels on respective positive and negative differential signal lines of each input analog signal channel; and combining the plurality of input analog signal channels into a single output analog signal channel in an analog multiplexer comprising a plurality of input sampling circuits associated with respective ones of the input analog signal channels and a differential amplifier having positive and negative inputs controllably connectable in turn to each of the input sampling circuits; wherein in conjunction with the combining step at least a given one of the input analog signal channels is connected to a sampling element of its corresponding input sampling circuit at a predetermined time prior to connecting the sampling element of that input sampling circuit to the input of the amplifier; wherein the predetermined time is less than a full clock cycle of a sampling clock of the amplifier; and
wherein the combining further comprises;coupling positive and negative differential signal lines of a corresponding input analog signal channel with first plates of first and second sampling capacitors through closed first and second switches while second plates of the first and second sampling capacitors are coupled to a common mode voltage reference through closed third and forth switches and while open fifth and sixth switches decouple the second plates from respective positive and negative inputs of the differential amplifier; sampling the positive and negative input signals through closed fifth and sixth switches coupling the second plates of the first and second sampling capacitors to the respective positive and negative inputs of the differential amplifier while open third and fourth switches decouple the second plates from the common mode voltage; and opening the first and second switches to decouple the first plates of first and second sampling capacitors from the input analog signal channel while charge is transferred from the first and second capacitors for amplification by the differential amplifier. - View Dependent Claims (14)
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15. An image sensor comprising:
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a pixel array; and readout circuitry coupled to the pixel array; the readout circuitry comprising an analog multiplexer configured to multiplex a plurality of input analog signal channels into a single output analog signal channel; the analog multiplexer comprising a plurality of input sampling circuits associated with respective ones of the input analog signal channels and a differential amplifier having positive and negative inputs controllably connectable in turn to each of the input sampling circuits, the sampling circuits each comprising positive and negative inputs coupled to respective positive and negative differential signal lines of a corresponding input analog signal channel; wherein the analog multiplexer is further configured to connect the positive and negative inputs of a given input sampling circuit to respective first plates of respective first and second sampling capacitors at the predetermined time prior to connecting respective second plates of the first and second sampling capacitors to the respective positive and negative inputs of the differential amplifier; wherein the predetermined time is less than a full clock cycle of a sampling clock of the amplifier; and wherein the given input sampling circuit comprises; a positive signal path having a first switch coupled between the positive input of the input sampling circuit and a first plate of a first sampling capacitor; a negative signal path having a second switch coupled between the negative input of the input sampling circuit and a first plate of a second sampling capacitor; third and fourth switches coupled between respective second plates of the first and second sampling capacitors and a common mode voltage reference; and fifth and sixth switches arranged in series with the respective first and second switches and the respective first and second sampling capacitors in the respective positive and negative signal paths and coupled between the respective second plates of the first and second sampling capacitors and the respective positive and negative inputs of the differential amplifier. - View Dependent Claims (16, 17)
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Specification