Pseudo digital gain control for broadband tuner

• US 8,184,206 B2
• Filed: 11/07/2006
• Issued: 05/22/2012
• Est. Priority Date: 11/07/2006
• Status: Active Grant

• Current Assignee: CSR Technology Incorporated (Qualcomm, Inc.)
• Original Assignee: CSR Technology Incorporated (Qualcomm, Inc.)
• Inventors: Magnusen, Timothy M.
• Primary Examiner(s): Tran, Trang U
• Application Number:
  US11/557,307
• Publication Number:
  US 20080125068A1
• Time in Patent Office: 2,023 Days
• Field of Search: 348725-726, 348/731, 348/678, 348/607, 348/720, 455/315, 455/339, 455/302, 455/232.1, 455/234.1, 455/234.2, 455/253.2, 327261-263, 327/157, 327/536, 327/268, 327/283, 327/290, 327/379, 330/279, 330/284
• US Class Current: 348/678
• CPC Class Codes: H03G 1/0088 using discontinuously variable devices, e.g. switch-operated
• CPC Class Codes: H03G 3/001 Digital control of analog signals

Abstract

A digital level control circuit, such as an Automatic Gain Control, includes a plurality of digitally selectable signal levels with transitions between levels gradually varied to avoid signal output level discontinuities. An up/down counter may be used to incrementally stepwise transition an output signal between the digitally selectable output levels. Stepwise application of a control signal to the appropriate switching elements (e.g., FETs) forming an attenuator circuit may be implemented to moderate a switching time of the switching elements to provide a more gradual transition between element operating states. A deglitch circuit may be employed to latch the switching elements to achieve the desired state at the end of a desired switching transition period.

Claims

1. A circuit comprising:

a digital control circuit responsive to a digital control signal for providing a plurality of discrete selector signals;

a level control circuit responsive to said discrete selector signals for controlling a level of an input signal to provide an output signal;

a moderating circuit connected to said digital control circuit and said level control circuit for moderating a transition in said level of said input signal between signal levels, wherein said moderating circuit transmits each of said discrete selector signals from said digital control circuit to said level control circuit as a sequence of intermediate incremental changes in response to each change in level initiated by said digital control circuit; and

a plurality of latch circuits, each connected to transmit a respective one of said discrete selector signals to said level control circuit and configured to latch said discrete selector signals to a selected level upon completion of a level transition period, wherein said plurality of latch circuits remain passive during a transition in said level.

2. The circuit of claim 1 wherein said moderating circuit is responsive to a count signal for incrementally stepping said level of said input signal between an initial level and a final level corresponding to a change in said digital control signal.

3. The circuit of claim 1 wherein said plurality of latch circuits is configured to drive elements within said level control circuit into saturation after a level transition period is complete.

4. The circuit of claim 1 wherein said a moderating circuit transitions said level of said input signal over a transition period sufficient to maintain signal level discontinuities at or below a maximum acceptable level.

5. The circuit according to claim 1, said level control circuit comprising an attenuator circuit connected to receive said discrete selector signal and, in response, selectively attenuating said input signal to maintain a desired level of said output signal.

6. The circuit according to claim 1 wherein said level control circuit comprises a plurality of switching elements each connected to receive and responsive to a respective one of said discrete selector signals.

7. A circuit comprising:

a digital switch including a plurality of switching elements, said digital switch responsive to a digital control signal for controlling said switching elements to control a level of an output signal to one of a plurality of selectable level values;

a moderating circuit connected to said switching elements and supplying an analog control signal thereto so as to cause said switching elements to transition between conducting states in response to said digital control signal over an appropriate period of time; and

a deglitch circuit connected to said moderating circuit and to said switching elements of said digital switch, said deglitch circuit configured to coordinate control signals between said moderating circuit and said switching elements such that a minimum number of transitions are permitted to occur at one time.

8. The circuit of claim 7 wherein said appropriate period of time is greater than a maximum switching time of said switching elements and of a signal rise time of said digital control signal.

9. The circuit according to claim 7, said digital switch comprising an attenuator circuit connected to receive an output from a signal source and, responsive to said digital signal, attenuate said output to achieve said desired level.

10. The circuit according to claim 7 wherein said deglitch circuit is configured to latch said switching elements in respective operating states responsive to said digital control signal at an end of said appropriate period of time.

11. The circuit according to claim 7, said moderating circuit comprising:

a plurality of switching elements responsive to a timing signal for providing said analog control signal with a monotonically changing level.

12. The circuit according to claim 7 further comprising a deglitch circuit for latching a level of said analog control signal to an appropriate terminal output level at an end of said appropriate period of time.

13. The circuit according to claim 7 further comprising a counter selectively operable in a count-up and count-down mode of operation for causing said level of said analog control signal to selectively monotonically increase and monotonically decrease between first and second levels through a plurality of intermediate levels.

14. The circuit according to claim 7 further comprising a deglitch circuit connected to said digital switch and said moderating circuit and configured to latch said switching elements in states appropriate for supplying a desired output signal level at an end of said appropriate period of time.

15. The circuit according to claim 7 further comprising a control circuit connected to receive said output signal and, in response to a level thereof, cause said digital switch to adjust said level to achieve a desired level.

16. The circuit according to claim 7 wherein said digital switch comprises an attenuator circuit.

17. The circuit of claim 7 wherein said deglitch circuit is configured to coordinate control signals between said moderating circuit and said switching elements such that a only one transition is permitted to occur at one time.

18. A circuit for controlling an output level of a signal comprising:

a plurality of switching elements connected to receive an input signal and selectively control a level of said input signal to provide an output signal;

a moderating circuit connected to said switching elements, said moderating circuit including a counter and selectively providing a monotonically changing signal level to a switching element of said switching elements in response to said counter to cause said switching element to change conduction states over some finite transition period, whereby said switching element incrementally transitions between an open and close conduction state; and

a plurality of latch circuits connected between said plurality of switching elements and said moderating circuit configured to latch a selected level to said plurality of switching elements upon completion of a transition period, wherein said plurality of latch circuits remain passive during a transition in said level.

19. A tuner comprising:

a radio frequency (RF) input stage;

an RF converter stage connected to said RF input stage and receiving an RF signal therefrom to provide an intermediate frequency (IF) signal;

an IF stage including an automatic gain control circuit (A.G.C.), said A.G.C. including;

(i) a digital control circuit responsive to a digital control signal for providing a plurality of discrete selector signals;

(ii) a level control circuit responsive to said discrete selector signals for controlling a level of said IF signal; and

(iii) a moderating circuit connected to said digital control circuit and said level control circuit for moderating a transition in said level of said IF signal between signal levels, wherein said moderating circuit transmits each of said discrete selector signals from said digital control circuit to said level control circuit as a sequence of intermediate incremental changes to cause switching elements of the level control circuit to incrementally transition between open and close conduction states; and

a signal detector demodulating said IF signal to provide an output signal.