Semiconductor apparatus

• US 8,184,463 B2
• Filed: 12/13/2009
• Issued: 05/22/2012
• Est. Priority Date: 12/18/2008
• Status: Expired due to Fees

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Saen, Makoto, Osada, Kenichi, Yamaoka, Masanao, Sekiguchi, Tomonori
• Primary Examiner(s): Pham, Ly D
• Application Number:
  US12/636,758
• Publication Number:
  US 20100155921A1
• Time in Patent Office: 891 Days
• Field of Search: 365/63, 257/777
• US Class Current: 365/63
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA

Abstract

The need for mediation operation is eliminated by adoption of a connection topology in which a circuit for executing one transmission (TR_—00T), and a circuit for executing a plurality of receptions (TR_—10R, TR_—20R, TR_—30R) are connected to one penetration-electrode group (for example, TSVGL_—0). In order to implement the connection topology even in the case of piling up a plurality of LSIs one after another, in particular, a programmable memory element for designating respective penetration-electrode ports for use in transmit, or for us in receive, and address allocation of the respective penetration-electrode ports is mounted in stacked LSIs.

Claims

1. A semiconductor apparatus comprising:

first, second, and third semiconductor chips piled up one after another; and

first, second, and third penetration-electrode groups for establishing communication among the first to the third semiconductor chips,

wherein the first semiconductor chip transmits a request signal to the second semiconductor chip via the first penetration-electrode group, and the second semiconductor chip sends back a response signal to the first semiconductor chip via the second penetration-electrode group in response to the request signal, and

wherein the first semiconductor chip transmits a request signal to the third semiconductor chip via the first penetration-electrode group, and the third semiconductor chip sends back a response signal to the first semiconductor chip via the third penetration-electrode group in response to the request signal.

2. The semiconductor apparatus according to claim 1,

wherein the first semiconductor chip includes:

a first transmit/receive circuit serving as an interface with the first penetration-electrode group;

a second transmit/receive circuit serving as an interface with the second penetration-electrode group;

a third transmit/receive circuit serving as an interface with the third penetration-electrode group; and

a first transmit/receive setting unit for executing setting to the first, second, and third transmit/receive circuits, respectively;

wherein the second semiconductor chip includes;

a fourth transmit/receive circuit serving as an interface with the first penetration-electrode group;

a fifth transmit/receive circuit serving as an interface with the second penetration-electrode group;

a sixth transmit/receive circuit serving as an interface with the third penetration-electrode group; and

a second transmit/receive setting unit for executing setting to the fourth, fifth, and sixth transmit/receive circuits, respectively; and

wherein the third semiconductor chip includes;

a seventh transmit/receive circuit serving as an interface with the first penetration-electrode group;

a eighth transmit/receive circuit serving as an interface with the second penetration-electrode group;

a ninth transmit/receive circuit serving as an interface with the third penetration-electrode group; and

a third transmit/receive setting unit for executing setting to the seventh, eighth, and ninth transmit/receive circuits, respectively; and

wherein the first transmit/receive setting unit setting the first transmit/receive circuit as a dedicated transmit circuit, the second transmit/receive circuit as a dedicated receive circuit, and the third transmit/receive circuit as a dedicated receive circuit, respectively,

wherein the second transmit/receive setting unit setting the fourth transmit/receive circuit as a dedicated receive circuit, the fifth transmit/receive circuit as a dedicated transmit circuit, and the sixth transmit/receive circuit as a dedicated receive circuit, respectively, and

wherein the third transmit/receive setting unit setting the seventh transmit/receive circuit as a dedicated receive circuit, the eighth transmit/receive circuit as a dedicated receive circuit, and the ninth transmit/receive circuit as a dedicated transmit circuit, respectively.

3. The semiconductor apparatus according to claim 2, wherein the first, second, and third transmit/receive setting units each are realized by use of a programmable memory element.

4. The semiconductor apparatus according to claim 2,

wherein the first semiconductor chip further includes:

a first processing block with a first identifier assigned thereto, and a first path-setting unit;

wherein the second semiconductor chip further includes;

a second processing block with a first address assigned thereto, and a second path setting unit; and

wherein the third semiconductor chip further includes;

a third processing block with a second address assigned thereto, and a third path-setting unit,

wherein the request signal includes an address indicating a destination, and an identifier indicating a request source,

wherein the first path setting unit executes path setting such that the request signal from the first processing block toward the first address, and the request signal from the first processing block toward the second address are connected to the first transmit/receive circuit,

wherein the second path setting unit executes path setting such that the response signal from the second processing block toward the first identifier is connected to the fifth transmit/receive circuit, and

wherein the third path setting unit executes path setting such that the response signal from the third processing block toward the first identifier is connected to the ninth transmit/receive circuit.

5. The semiconductor apparatus according to claim 4,

wherein the first, second, and third path setting units each are realized by use of a plurality of switch circuits, and a programmable memory element for setting ON/OFF of the plurality of the switch circuits.

6. The semiconductor apparatus according to claim 1,

wherein the first semiconductor chip transmits a trigger signal in parallel with data signal indicating contents of a request, as the request signal, and

wherein the second semiconductor chip or the third semiconductor chip fetches the data signal therein by use of the trigger signal.

7. The semiconductor apparatus according to claim 2,

wherein the first, second, and third semiconductor chips each include a processor circuit, and

wherein setting in the first, second, and third transmit/receive setting units, respectively, is executed on the basis of a program of the processor circuit.

8. The semiconductor apparatus according to claim 1,

wherein the first, second, and third semiconductor chips each includes a memory element for storing a chip identifier, and

wherein the chip identifier is set to variously different values for each of the first, second, and third semiconductor chips by writing according to a shift-chain configuration via a penetration-electrode.

9. A semiconductor apparatus comprising a first semiconductor chip for use with other semiconductor chips piled up one after another thereon, the first semiconductor chip including:

first, second, and third penetration-electrode port groups;

first to third transmit/receive circuits connected to the first, second, and third penetration-electrode port groups, respectively; and

a transmit/receive setting unit for executing setting to the first, second, and third transmit/receive circuits, respectively,

wherein the transmit/receive setting unit sets the first transmit/receive circuit to a dedicated transmit circuit in order to transmit a request signal to those other semiconductor chips including second and third semiconductor chips, sets the second semiconductor chip to a dedicated receive circuit in order to receive a response to the request signal from the second semiconductor chip, and sets the third semiconductor chip to a dedicated receive circuit in order to receive a response to the request signal from the third semiconductor chip.

10. The semiconductor apparatus according to claim 9,

wherein the transmit/receive setting unit is realized by use of a programmable memory element.

11. The semiconductor apparatus according to claim 9,

wherein the first semiconductor chip further includes a processing block for executing a predetermined processing, and a path setting unit, and

wherein the path setting unit executes setting such that an output from the processing block is connected to the first transmit/receive circuit and executes setting such that an input from the second transmit/receive circuit and an input from the third transmit/receive circuit are connected to an input of the processing block.

12. The semiconductor apparatus according to claim 11,

wherein the path setting unit is realized by use of a plurality of switch circuits, and a programmable memory element for setting ON/OFF of the plurality of the switch circuits.

13. A semiconductor apparatus comprising:

a plurality of semiconductor chips piled up one after another to be mounted therein; and

a plurality of penetration-electrodes for use in establishing communication among the plurality of the semiconductor chips,

wherein the plurality of the semiconductor chips each including;

a plurality of transmit/receive circuits each serving as an interface with each of the plurality of the penetration-electrodes; and

a transmit/receive setting unit for setting each of the plurality of the transmit/receive circuits to a dedicated transmit circuit, or a dedicated receive circuit,

wherein the transmit/receive setting unit executes setting such that one of the dedicated transmit circuits, and a plurality of the dedicated receive circuits are connected to each of the plurality of the penetration-electrodes.

14. The semiconductor apparatus according to claim 13,

wherein the transmit/receive setting unit is realized by use of a programmable memory element.

15. The semiconductor apparatus according to claim 13,

wherein the plurality of the semiconductor chips include first and second semiconductor chips,

wherein the plurality of the penetration-electrodes include first and second penetration-electrodes,

wherein the first semiconductor chip includes:

a first processing block including a first request processing circuit, and a first response processing circuit;

a first dedicated transmit circuit set by the transmit/receive setting unit, connected to a first penetration-electrode;

a first dedicated receive circuit set by the transmit/receive setting unit, connected to a second penetration-electrode; and

a first path setting unit,

wherein the second semiconductor chip includes;

a second processing block having a second request processing circuit, and a second response processing circuit;

a second dedicated receive circuit set by the transmit/receive setting unit, connected to the first penetration-electrode;

a second dedicated transmit circuit set by the transmit/receive setting unit, connected to the second penetration-electrode; and

a second path setting unit,

wherein the first path setting unit executes setting such that an output from the first request processing circuit is connected to the first dedicated transmit circuit, an input from the second response processing circuit to the first dedicated receive circuit is connected to the first request processing circuit, and an input from the second request processing circuit to the first dedicated receive circuit is connected to the first response processing circuit, and

wherein the second path setting unit executes setting such that an output from the second request processing circuit is connected to the second dedicated transmit circuit, an input from the first response processing circuit to the second dedicated receive circuit is connected to the second request processing circuit, and an input from the first request processing circuit to the second dedicated receive circuit is connected to the second response processing circuit.

16. The semiconductor apparatus according to claim 15,

wherein the first and second path setting units each are realized by use of a plurality of switch circuits, and a programmable memory element for setting ON/OFF of the plurality of the switch circuits.