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  • US 8,185,666 B2
  • Filed: 04/28/2005
  • Issued: 05/22/2012
  • Est. Priority Date: 07/27/2004
  • Status: Active Grant
First Claim
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1. A processor executing a plurality of instructions, comprising:

  • an arithmetic logic unit (ALU); and

    a plurality of registers coupled to the ALU;

    wherein said processor executes an instruction that causes a first comparison to be performed between contents of a first register and contents of a second register and a second comparison to be performed between the contents of the first register and a predetermined value; and

    wherein the instruction causes a first status bit to be set if either of said comparisons results in a true condition and a second status bit to be set if the first comparison determines that the contents of the first register equal the contents of the second register.

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