Virtual memory window with dynamic prefetching support

• US 8,185,696 B2
• Filed: 04/19/2005
• Issued: 05/22/2012
• Est. Priority Date: 04/20/2004
• Status: Expired due to Fees

• Current Assignee: Ecole polytechnique fãdãrale de lausanne epfl (Schweizerische Eidgenossenschaft)
• Original Assignee: Ecole polytechnique fãdãrale de lausanne epfl (Schweizerische Eidgenossenschaft)
• Inventors: Vuletic, Miljan, Pozzi, Laura, Ienne, Paolo
• Primary Examiner(s): NGUYEN, THAN VINH
• Application Number:
  US11/578,830
• Publication Number:
  US 20100005272A1
• Time in Patent Office: 2,590 Days
• Field of Search: None
• US Class Current: 711/137
• CPC Class Codes: G06F 12/1081 for peripheral access to main memory, e.g. direct memory access [DMA]
• CPC Class Codes: G06F 9/3877 using a slave processor, e.g. coprocessor peripheral processor G06F13/12; vector processor G06F15/8053

Abstract

Reconfigurable Systems-an-Chip (RSoCs) on the market consist of full-fledged processors and large Field-Programmable Gate Arrays (FPGAs). The latter can be used to implement the system glue logic, various peripherals, and application-specific coprocessors. Using FPGAs for application-specific coprocessors has certain speedup potentials, but it is less present in practice because of the complexity of interfacing the software application with the coprocessor. In the present application, we present a virtualisation layer consisting of an operating system extension and a hardware component. It lowers the complexity of interfacing and increases portability potentials, while it also allows the coprocessor to access the user virtual memory through a virtual memory window. The burden of moving data between processor and coprocessor is shifted from the programmer to the operating system.

Claims

1. A processing system comprising:

at least a central unit;

a main memory; and

a peripheral, this peripheral accessing the main memory at peripheral predefined addresses, and the central unit accessing the peripheral at central unit predefined addresses, wherein the access to the main memory by the peripheral is made through an abstract identifier manager, said manager converting the peripheral predefined addresses to the central unit predefined addresses while accessing the main memory, and wherein the system further comprises;

a shared memory usable by both the central unit and the peripheral, said manager being configured to copy data objects or fragments thereof needed by the peripheral between the shared memory and the main memory; and

additional analysing means to predict useful data objects or fragments thereof for the peripheral and comprises additional buffer means in the shared memory to copy in advance such objects or fragments thereof to and from the shared memory.

2. The processing system of claim 1 wherein the analysing means further comprises means to validate or confute the past prediction.

3. The processing system of claim 1 wherein the analysing means further comprises means to schedule future page loads into a fetch queue.

4. The processing system of claim 1 wherein the analysing means detects the needed data from the central unit predefined address.

5. The processing system of claim 1 wherein the analysing means further comprises a history memory which is used to predict the data to be copied in advance.

6. The processing system of claim 1 wherein the analysing means further comprises detecting means to detect a pointer address into the data returned to the peripheral and load in advance the data pointed by said address.