Methods and systems for coherence protocol tuning

• US 8,185,697 B1
• Filed: 01/07/2005
• Issued: 05/22/2012
• Est. Priority Date: 01/07/2005
• Status: Active Grant

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Collard, Jean-Francois, Yehia, Sami
• Primary Examiner(s): Rojas, Midys
• Application Number:
  US11/030,937
• Time in Patent Office: 2,692 Days
• Field of Search: 711/141
• US Class Current: 711/141
• CPC Class Codes: G06F 12/0815 Cache consistency protocols

Abstract

A method and system for selectively applying one of a plurality of different memory coherence protocols are described. When an application is executed to generate a memory access transaction, a table can be evaluated to determine whether the transaction should be processed in accordance with a first memory coherence protocol or a second memory coherence protocol. Then, the transaction can be processed according to the selected memory coherence protocol. Alternatively, or in conjunction therewith, the application can be modified to execute more efficiently on a particular memory coherence protocol.

Claims

1. A method for selectively applying one of a plurality of different memory coherence protocols comprising the steps of:

executing an application in a processing system;

receiving a transaction that involves a memory access;

evaluating a table to determine whether said transaction should be processed in accordance with a first memory coherence protocol or a second memory coherence protocol, wherein said first memory coherence protocol is different than said second memory coherence protocol; and

processing said transaction using a selected one of said first and second memory coherence protocols.

2. The method of claim 1, further comprising the steps of:

storing, in said table, information including at least one of;

target address information, instruction pointer information and processor ID information;

responding to said transaction using said first memory coherence protocol if said transaction does not generate a match with said information in said table; and

otherwise, responding to said transaction using said second memory coherence protocol.

3. The method of claim 2, wherein said table is provided in a cell controller associated with at least one processor and at least one memory device.

4. The method of claim 2, wherein said step of storing, in said table, information including at least one of:

target address information, instruction pointer information and processor ID information further comprises the step of;

executing said application on said processing system using said first memory coherence protocol;

identifying transactions within said application which execute inefficiently when using said first memory coherence protocol; and

storing information associated with said identified transactions in said table.

5. The method of claim 4, wherein said step of executing said application further comprises the step of:

executing said application on a simulator.

6. The method of claim 4, wherein said step of executing said application further comprises the step of:

executing said application on another processing system which includes a mechanism for correlating coherence protocol events with instructions in said application.

7. The method of claim 4, wherein said step of executing said application further comprises the step of:

generating a sequence of coherence requests sent by each processor, together with an associated pointer to an instruction which caused each coherence request and an address of target data associated therewith.

8. The method of claim 4, wherein said step of identifying transactions within said application which execute inefficiently further comprises the step of

identifying a specific transaction sequence generated by said application.

9. The method of claim 8, wherein said specific transaction sequence pattern is a read request, followed by a write request, wherein both said read request and said write request are sent by a same processor and target a same cache line.

10. The method of claim 4, further comprising the step of:

modifying said application to insert at least one instruction before an instruction associated with one of said identified transactions.

11. The method of claim 4, further comprising the step of:

modifying said application to replace an instruction associated with an identified transaction with another instruction, wherein said another instruction implements an aspect of said second memory coherence protocol.

12. The method of claim 1, wherein said first and second memory coherence protocol describe how and which memory devices will be updated when a write operation is performed.

13. A processing system for processing data in accordance with one of a plurality of memory coherence protocols comprising:

a plurality of processors for initiating transactions within said processing system;

a plurality of tables which contain instruction identification information; and

a plurality of controllers which selectively return responses to said transactions according to either a first memory coherence protocol or a second memory coherence protocol depending upon whether a respective transaction includes data which matches a table entry.

14. The processing system of claim 13, wherein said instruction identification information includes at least one of:

target address information, an instruction pointer and a processor ID.

15. The processing system of claim 13, wherein said first and second memory coherence protocol describe how and which memory devices will be updated when a write operation is performed.

16. A processing system for processing data in accordance with one of a plurality of memory coherence protocols comprising:

means for initiating transactions within said processing system;

means for storing instruction identification information; and

means for selectively responding to said transactions according to either a first memory coherence protocol or a second memory coherence protocol depending upon whether a respective transaction includes data which matches a table entry.

17. The processing system of claim 16, wherein said instruction identification information includes at least one of:

target address information, an instruction pointer and a processor ID.

18. The processing system of claim 16, wherein said first and second memory coherence protocol describe how and which memory devices will be updated when a write operation is performed.

19. A method for selectively applying one of a plurality of different memory coherence protocols comprising the steps of:

executing an application in a processing system;

receiving a request that involves a memory access;

determining whether said request should be processed in accordance with a first memory coherence protocol or a second memory coherence protocol, wherein said first memory coherence protocol is different than said second memory coherence protocol, in order to execute said request efficiently; and

processing said transaction using a selected one of said first and second memory coherence protocols.

20. The method of claim 19, wherein said step of determining further comprises the step of:

selecting a one of said first memory coherence protocol and said second memory coherence protocol which will result in said request being executed using a least number of transactions.

21. The method of claim 19, wherein said determining step further comprises the step of:

evaluating a table to determine whether said request should be processed in accordance with said first memory coherence protocol or said second memory coherence protocol.

22. The method of claim 19, wherein said step of processing said transaction further comprises the step of:

modifying said application based on said step of determining to implement either said first memory coherence protocol or said second memory coherence protocol for said request.

23. The method of claim 19, wherein said first and second memory coherence protocol describe how and which memory devices will be updated when a write operation is performed.