Flexible sequencer design architecture for solid state memory controller

• US 8,185,713 B2
• Filed: 09/17/2008
• Issued: 05/22/2012
• Est. Priority Date: 09/19/2007
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell World Trade Limited (Marvell Technology Group Limited)
• Inventors: Shin, Hyunsuk, Lee, Chi Kong, Yoon, Tony
• Primary Examiner(s): DOAN, DUC T
• Application Number:
  US12/212,636
• Publication Number:
  US 20090077305A1
• Time in Patent Office: 1,343 Days
• Field of Search: None
• US Class Current: 711/167
• CPC Class Codes: G06F 13/1668 Details of memory controller
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays

Abstract

A method and apparatus for controlling access to solid state memory devices which may allow maximum parallelism on accessing solid state memory devices with minimal interventions from firmware. To reduce the waste of host time, multiple flash memory devices may be connected to each channel. A job/descriptor architecture may be used to increase parallelism by allowing each memory device to operate separately. A job may be used to represent a read, write or erase operation. When firmware wants to assign a job to a device, it may issue a descriptor, which may contain information about the target channel, the target device, the type of operation, etc. The firmware may provide descriptors without waiting for a response from a memory device, and several jobs may be issued continuously to form a job queue. After the firmware finishes programming descriptors, a sequencer may handle the remaining work so that the firmware may concentrate on other tasks.

Claims

1. A method for controlling access to solid state memory devices, wherein the solid state memory devices are coupled to a controller, and the controller is controlled using firmware, the method comprising:

receiving, from a host, a first operation request and a second operation request;

programming, using the firmware, a first descriptor for the first operation request and a second descriptor for the second operation request;

sequencing the first descriptor and the second descriptor via a sequencer;

transferring first data, according to the first descriptor, from a first solid state memory device of the solid state memory devices to the controller;

determining whether the transferring of the first data according to the first descriptor has completed; and

if the transferring of the first data according to the first descriptor has completed, starting a transfer of second data, according to the second descriptor, (i) sequentially after the transferring of the first data, and (ii) from a second solid state memory device of the solid state memory devices to the controller, wherein the second data is transferred to the controller while the first data is being transferred from the controller to the host,

wherein the sequencer comprises an auxiliary first-in-first-out buffer configured to receive, from a device executing the firmware, logical block address information about data to be transferred.

2. The method of claim 1, wherein the first descriptor includes information about a target device, a target channel, and a type of operation.

3. The method of claim 1, further comprising providing the first descriptor without waiting for a response from a memory device.

4. The method of claim 1, wherein the first descriptor and the second descriptor are provided continuously to form a job queue.

5. The method of claim 4, further comprising placing the first descriptor and the second descriptor in a track.

6. The method of claim 5, wherein the track has 16 descriptors.

7. The method of claim 6, wherein a T-bit of the 16^th descriptor is set.

8. The method of claim 5, further comprising determining whether there is another descriptor to be performed in the track.

9. The method of claim 5, further comprising, when all descriptors in a track are completed, generating an interrupt signal and transmitting the interrupt signal to a device executing the firmware.

10. The method of claim 1, further comprising checking availability of a target device before issuing the first descriptor.

11. The method of claim 1, further comprising reporting status of the first operation request and the second operation request to a device executing the firmware.

12. The method of claim 1, wherein the first operation request is a write request, and the first solid state memory device comprises an internal buffer of a target device.

13. The method of claim 12, further comprising performing an error correction parity calculation on data received from the host.

14. The method of claim 1, wherein the first operation request is a read request, and the first solid state memory device comprises an internal buffer of a target device to the controller.

15. The method of claim 14, further comprising storing a logical block address of requested data.

16. The method of claim 14, further comprising performing error correction coding on data received from the host.

17. The method of claim 14, further comprising formatting data transmitted to or received from the host to conform with requirements of the host.

18. The method of claim 1, wherein an amount of time for finishing the data transfer is shorter than an amount of time for finishing the first operation.

19. A method for controlling access to solid state memory devices, wherein the solid state memory devices are coupled to a controller, and the controller is controlled using firmware, the method comprising:

receiving at least a first operation request and a second operation request from a host, wherein the first operation request is a read request;

programming, using the firmware, a first descriptor for the first operation request and a second descriptor for the second operation request;

sequencing the first descriptor and the second descriptor;

transferring first data according to the first descriptor from an internal buffer of a target device to the controller;

determining whether the transferring of the first data according to the first descriptor has finished;

starting to transfer second data according to the second descriptor if the transferring of the first data according to the first descriptor has completed;

storing a logical block address of requested data; and

comparing the stored logical block address and a logical block address of the first data obtained from the target device according to the first descriptor.

20. An apparatus for controlling access to solid state memory devices, the apparatus comprising:

firmware for programming i) a first descriptor for a first operation request and ii) a second descriptor for a second operation request;

a sequencer for receiving the first descriptor and the second descriptor; and

a flash controller coupled to the sequencer and to the solid state memory devices, wherein the flash controller is configured to

(i) receive the first descriptor, the second descriptor, and instructions from the sequencer, and

(ii) transfer first data according to the first descriptor from a first solid state memory device of the solid state memory devices to the flash controller, wherein the instructions include read requests for transferring the first data and second data,

wherein the flash controller is configured to start to transfer the second data, according to the second descriptor, from a second solid state memory device of the solid state memory devices to the flash controller when the transferring of the first data according to the first descriptor has finished,

wherein, prior to the transferring of the first data according to the first descriptor being completed, (i) the flash controller is configured to transmit one of the read requests for the second data to the second solid state memory device, and (ii) the second solid state memory device is configured to transfer the second data to an internal buffer of the second solid state memory device according to the one of the read requests, and

wherein the sequencer further comprises an auxiliary first-in-first-out buffer configured to receive, from a device executing the firmware, logical block address information about data to be transferred.

21. The apparatus of claim 20, wherein the first descriptor includes information about a target memory device, a target channel, and a type of the operation.

22. The apparatus of claim 20, wherein the sequencer further comprises a descriptor first-in-first-out buffer, configured to receive the first descriptor and the second descriptor from a device executing the firmware.

23. The apparatus of claim 20, further comprising an error correction unit configured to perform error correction coding on data received from a host.

24. The apparatus of claim 20, further comprising a formatter configured to format data from a host to conform with requirements of the flash controller.

25. The apparatus of claim 20, wherein a device executing the firmware provides the first descriptor without waiting for a response from a memory device.

26. The apparatus of claim 20, wherein a device executing the firmware provides the first descriptor and the second descriptor continuously to form a job queue.

27. The apparatus of claim 20, wherein the sequencer checks availability of a target device before issuing the first descriptor to the flash controller.

28. The apparatus of claim 27, wherein the sequencer informs the flash controller to be ready for the type of the operation.

29. The apparatus of claim 20, wherein the sequencer reports a status of operations to a device executing the firmware.

30. The apparatus of claim 20, wherein an amount of time for finishing the data transfer is shorter than an amount of time for finishing the first operation.

31. The apparatus of claim 20, wherein the flash controller is configured to transfer the second data from the internal buffer to the flash controller upon completing the transferring of the first data according to the first descriptor.

32. The apparatus of claim 20, wherein the sequencer comprises:

an auxiliary first-in-first-out buffer configured to store auxiliary data for error correction coding; and

a descriptor first-in-first-out buffer configured to store a plurality of descriptors including the first descriptor and the second descriptor,

wherein the flash controller accesses the solid state memory devices according to a physical block of the second descriptor while performing error correction coding operations according to a logical block of the auxiliary data associated with the first data.

33. The apparatus of claim 30, wherein the flash controller transfers the second data according to the second descriptor from the second solid state memory device to the flash controller while formatting the first data received from the first solid state memory device.

34. The apparatus of claim 20, wherein the first operation request is a read request, and the first solid state memory device comprises an internal buffer of a target device.