Self-referencing communication in implantable devices

• US 8,187,161 B2
• Filed: 08/29/2008
• Issued: 05/29/2012
• Est. Priority Date: 08/31/2007
• Status: Active Grant

• Current Assignee: Proteus Digital Health, Inc. (Otsuka Holdings Company Limited)
• Original Assignee: Proteus Biomedical, Inc. (Otsuka Holdings Company Limited)
• Inventors: Li, Haifeng, Zdeblick, Mark, Arne, Lawrence, Bi, Yafei, Jani, Nilay, Withrington, Jonathan
• Primary Examiner(s): Patel, Niketa
• Assistant Examiner(s): FAIRCHILD, MALLIKA DIPAYAN
• Application Number:
  US12/202,143
• Publication Number:
  US 20090062879A1
• Time in Patent Office: 1,369 Days
• Field of Search: 607/32, 607/60, 607/30, 128/903, 128/904
• US Class Current: 600/32
• CPC Class Codes: A61N 1/025 Digital circuitry features of electrotherapy devices, e.g. memory, clocks, processors
• CPC Class Codes: A61N 1/37288 Communication to several implantable medical devices within one patient

Abstract

Various aspects of the present invention enable robust, reliable control functionality for effectors present on intraluminal, e.g., vascular leads, as well as other types of implantable devices. Aspects of the invention include implantable integrated circuits that have self-referencing and self-clocking signal encoding, and are capable of bidirectional communication. Also provided by the invention are effector assemblies that include the integrated circuits, as well as implantable medical devices, e.g., pulse generators that include the same, as well as systems and kits thereof and methods of using the same, e.g., in pacing applications, including cardiac resynchronization therapy (CRT) applications.

Claims

1. An implantable system, comprising:

a controller comprising an amplifier and a first supply voltage, the amplifier comprising an input and an output;

first and second lead lines coupled to the controller, wherein the first and second lead lines are characterized at least by an impedance across the first and second lead lines;

a first variable resistor comprising first and second ends, wherein the first end of the first variable resistor is coupled to the first supply voltage and the second end of the first variable resistor is coupled to the first lead line, and wherein the first variable resistor is coupled to the input of the amplifier;

wherein the amplifier is configured to amplify a voltage difference across the first variable resistor; and

a plurality of implantable integrated circuits coupled to the first and second lead lines, wherein a selected one of said implantable integrated circuits is configured to reduce the impedance across the first and second lead lines to change the voltage difference across the first variable resistor to communicate an electrode configuration to the controller.

2. The implantable system of claim 1, further comprising detection logic coupled to the output of the amplifier, wherein the detection logic is configured to derive the electrode configuration.

3. The implantable system of claim 1, wherein the first variable resistor is changed to about 300Ω

for the amplification of the voltage difference.

4. The implantable system of claim 1, wherein the controller comprises a second supply voltage and a second variable resistor, the second variable resistor comprising first and second ends, wherein the first end of the second variable resistor is coupled to the second supply voltage and the second end of the second variable resistor is coupled to the second lead line.

5. The implantable system of claim 1, further comprising a transistor coupled between the first and second lead lines, wherein the impedance across the first and second lead lines is reduced by the transistor, wherein the transistor is enabled during a predetermined mode.

6. The implantable system of claim 1, further comprising first and second transistors coupled between the first and second lead lines, wherein the impedance across the first and second lead lines is reduced by the first and second transistors, wherein the first transistor is enabled during a predetermined mode, and the second transistor is enabled for a predetermined duration when entering the predetermined mode.