Direct contact in trench with three-mask shield gate process

• US 8,187,939 B2
• Filed: 09/23/2009
• Issued: 05/29/2012
• Est. Priority Date: 09/23/2009
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Inc. (Alpha & Omega Semiconductor, Ltd.)
• Original Assignee: Alpha & Omega Semiconductor, Inc. (Alpha & Omega Semiconductor, Ltd.)
• Inventors: Tai, Sung-Shan, Yilmaz, Hamza, Bhalla, Anup, Chang, Hong, Chen, John
• Primary Examiner(s): Dickey, Thomas L
• Assistant Examiner(s): YUSHIN, NIKOLAY K
• Application Number:
  US12/565,611
• Publication Number:
  US 20110068386A1
• Time in Patent Office: 979 Days
• Field of Search: 438/270, 438/589, 438/629, 438/268, 438/494, 438/689, 257/328, 257/330, 257/334, 257/E21.419, 257/E29.256
• US Class Current: 438/270
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/0869 Shape cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device and a method for making a semiconductor device are disclosed. A trench mask may be applied to a semiconductor substrate, which is etched to form trenches with three different widths. A first conductive material is formed at the bottom of the trenches. A second conductive material is formed over the first conductive material. An insulator layer separates the first and second conductive materials. A first insulator layer is deposited on top of the trenches. A body layer is formed in a top portion of the substrate. A source is formed in the body layer. A second insulator layer is applied on top of the trenches and the source. A contact mask is applied on top of the second insulator layer. Source and gate contacts are formed through the second insulator layer. Source and gate metal are formed on top of the second insulator layer.

Claims

1. A method for making a shield gate trench semiconductor device, comprising:

a) applying a trench mask as a first mask to a semiconductor substrate;

b) etching the semiconductor substrate to form trenches TR1, TR2 and TR3 with three widths W1, W2 and W3, respectively, wherein the trench TR3 is widest and deepest and the width W3 of the trench TR3 depends on a depth D2 of the trench TR2;

c) forming first conductive material at the bottom of the trenches TR1, TR2 and TR3 to form a source electrode;

d) forming a second conductive material over the first conductive material in the trenches TR1 and TR2 to form a gate electrode, wherein the first and second conductive materials are separated from each other and from the semiconductor substrate by an insulator material;

forming a dielectric layer on top of the source electrode in the trenches TR1, TR2 and TR3;

chemical mechanical polishing and/or etching back the dielectric layer to a pre-determined thickness to form the inter-poly-dielectric layer;

growing gate oxide on sidewalls of exposed portions of the trenches TR1, TR2 and TR3; and

depositing the second conductive material into the trenches TR1, TR2 and TR3 to a pre-determined thickness to fill up the trenches TR1 and TR2 but does not fill completely the trench TR3;

e) depositing a first insulator layer on top of the trenches TR1, TR2 and TR3, wherein a top portion of the trench TR3 is filled up with the insulator;

f) forming a body layer in a top portion of the substrate;

g) forming a source layer in a top portion of the body layer;

h) applying a second insulator layer on top of the trenches TR1, TR2 and TR3 and the source;

i) applying a contact mask as a second mask on top of the second insulator laver;

j) forming a source electrode contact in trench TR3, a gate electrode contact in trench TR2, and a source/body contact to the semiconductor substrate; and

k) applying a metal mask as a third mask and forming source metal and gate metal on top of the second insulator layer.

2. The method of claim 1 wherein the gate oxide has a thickness in a range from 250 Angstroms to 1000 Angstroms.

3. The method of claim 1 wherein the width W3 and the second conductive material is deposited in an amount selected such that there is a gap in the second conductive material deposited in the trench TR3.

4. The method of claim 3 wherein the gap is about 0.1 micron to 0.3 micron.

5. The method of claim 1, further comprising after g) and before h):

etching back the first insulator layer in the trenches TR1, TR2 and TR3 to form spacers; and

forming salicide on top of the second conductive material in the trenches TR1 and TR2 and on top of the source layer.

6. The method of claim 1 wherein k) comprises:

depositing a metal layer on top of the second insulator layer;

applying a metal mask as the third mask on top of the metal layer; and

etching the metal layer to form the gate metal and the source metal through the metal mask.

7. The method of claim 1, wherein a) comprises:

depositing an oxide layer on top of the semiconductor substrate; and

patterning the oxide layer with the first mask to form a hard mask.

8. The method of claim 1 wherein the W1 is about 0.3 micron to 0.5 micron;

W2 is about 0.6 micron to 0.9 micron; and

W3 is about 1.2 microns to 2.0 microns.

9. The method of claim 1, wherein a ratio W3/W2 is about 1.5 to 3.

10. The method of claim 1, wherein a ratio W3/D2 is about 1.1 to 1.3.

11. The method of claim 3, further comprising after d) and before e):

isotropically etching the second conductive material in the trenches TR1, TR2 and TR3 such that the second conductive material in the trench TR3 is completely removed, but wherein a portion of the second conductive material remains in the trenches TR1 and TR2.

12. The method of claim 11 wherein the second conductive material in the trenches TR1 and TR2 are recessed some degree to minimize a residue of the second conductive material in the trench TR3.

13. The method of claim 1 wherein c) comprises:

forming an oxide layer on sidewall of the trenches TR1, TR2 and TR3;

in-situ depositing the first conductive material into the trenches TR1, TR2 and TR3; and

etching back the first conductive material.

14. The method of claim 13 wherein a thickness of the oxide layer is about 1500 Angstroms to 2500 Angstroms.

15. The method of claim 1 wherein j) comprises:

selectively etching portions of the second insulator layer to form a source electrode contact hole and a gate electrode contact hole and a source/body contact hole;

depositing a barrier material on sidewall of the source electrode contact hole and gate electrode contact hole and source/body contact hole; and

filling up remaining portions of the source electrode contact hole and gate electrode contact hole and source/body contact hole with a conductive plug.

16. The method of claim 15, wherein the source electrode contact hole is larger than the gate electrode contact hole.

17. The method of claim 16, wherein the source electrode contact hole is about 0.35 micron to 0.7 micron in width and the gate electrode contact hole is about 0.25 micron to 0.35 micron in width.

29. The method of claim 15 wherein c) comprises:

forming an oxide layer on sidewall of the trenches TR1, TR2 and TR3;

in-situ depositing the first conductive material into the trenches TR1, TR2 and TR3; and

etching back the first conductive material.

30. The method of claim 29 wherein a thickness of the oxide layer is about 1500 Angstroms to 2500 Angstrom.

18. A method for making a shield gate trench semiconductor device, comprising:

a) applying a trench mask as a first mask to a semiconductor substrate;

b) etching the semiconductor substrate to form trenches TR1, TR2 and TR3 with three widths W1, W2 and W3, respectively, wherein the trench TR3 is widest and deepest and the width W3 of the trench TR3 depends on a depth D2 of the trench TR2;

c) forming first conductive material at the bottom of the trenches TR1, TR2 and TR3 to form a source electrode;

d) forming a second conductive material over the first conductive material in the trenches TR1 and TR2 to form a gate electrode, wherein the first and second conductive materials are separated from each other and from the semiconductor substrate by an insulator material;

e) depositing a first insulator layer on top of the trenches TR1, TR2 and TR3, wherein a top portion of the trench TR3 is filled up with the insulator;

f) forming a body layer in a top portion of the substrate;

g) forming a source layer in a top portion of the body layer;

h) applying a second insulator layer on top of the trenches TR1, TR2 and TR3 and the source;

i) applying a contact mask as a second mask on top of the second insulator laver;

j) forming a source electrode contact in trench TR3, a gate electrode contact in trench TR2, and a source/body contact to the semiconductor substrate; and

k) applying a metal mask as a third mask and forming source metal and gate metal on top of the second insulator layer;

further comprising, after e) and before f) selectively removing a portion of the first insulator layer to a level same as a top surface of the substrate.

19. The method of claim 18 wherein forming a body layer comprises vertical implantation and annealing.

20. The method of claim 18 wherein forming the source layer comprises vertical implantation and annealing.

21. The method of claim 18 wherein k) comprises:

depositing a metal layer on top of the second insulator layer;

applying a metal mask as the third mask on top of the metal layer; and

etching the metal layer to form the gate metal and the source metal through the metal mask.

22. The method of claim 18, wherein a) comprises:

depositing an oxide layer on top of the semiconductor substrate; and

patterning the oxide layer with the first mask to form a hard mask.

23. The method of claim 18 wherein the W1 is about 0.3 micron to 0.5 micron;

W2 is about 0.6 micron to 0.9 micron; and

W3 is about 1.2 microns to 2.0 microns.

24. The method of claim 18, wherein a ratio W3/W2 is about 1.5 to 3.

25. The method of claim 18, wherein a ratio W3/D2 is about 1.1 to 1.3.

26. The method of claim 18, further comprising after g) and before h):

etching back the first insulator layer in the trenches TR1, TR2 and TR3 to form spacers; and

forming salicide on top of the second conductive material in the trenches TR1 and TR2 and on top of the source layer.

27. The method of claim 18 wherein the first insulator layer is further recessed below the top surface of the substrate.

28. The method of claim 27, wherein forming the source layer comprises angled implantation and annealing.

31. The method of claim 18 wherein j) comprises:

selectively etching portions of the second insulator layer to form a source electrode contact hole and a gate electrode contact hole and a source/body contact hole;

depositing a barrier material on sidewall of the source electrode contact hole and gate electrode contact hole and source/body contact hole; and

filling up remaining portions of the source electrode contact hole and gate electrode contact hole and source/body contact hole with a conductive plug.

32. The method of claim 31, wherein the source electrode contact hole is larger than the gate electrode contact hole.

33. The method of claim 32, wherein the source electrode contact hole is about 0.35 micron to 0.7 micron in width and the gate electrode contact hole is about 0.25 micron to 0.35 micron in width.