Capacitor structure in trench structures of semiconductor devices and semiconductor devices comprising capacitor structures of this type and methods for fabricating the same

• US 8,187,947 B2
• Filed: 06/30/2010
• Issued: 05/29/2012
• Est. Priority Date: 09/13/2004
• Status: Expired due to Fees

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Mauder, Anton, Schulze, Hans-Joachim, Strack, Helmut
• Primary Examiner(s): Nguyen, Thinh T
• Application Number:
  US12/827,035
• Publication Number:
  US 20100264456A1
• Time in Patent Office: 699 Days
• Field of Search: 438/387, 438/386, 438/396, 438/397, 438/391, 257/139, 257/532
• US Class Current: 438/387
• CPC Class Codes: H01L 28/82 with an enlarged surface, e.g. formed by texturisation
• CPC Class Codes: H01L 29/66181 Conductor-insulator-semiconductor capacitors, e.g. trench capacitors
• CPC Class Codes: H10B 12/038 the capacitor being in a trench in the substrate

Abstract

A capacitor structure in trench structures of a semiconductor device includes conductive regions made of metallic and/or semiconducting materials. The conducting regions are surrounded by a dielectric and form stacked layers in the trench structure of the semiconductor device.

Claims

1. A method for fabricating a layered capacitor of a semiconductor device, the method comprising:

a) isotropically oxidizing and/or nitriding walls of a trench structure to provide wall protection;

b) anisotropically depositing a conductive material in the trench structure, a deposition rate at the walls being lower than at a bottom of the trench structure at least by at least a factor of two;

c) depositing a dielectric material in the trench structure on the conductive material, such that a deposition rate at the walls is lower than at the bottom of the trench structure;

d) producing a selective protective layer on a layer made of the dielectric material at the bottom of the trench structure;

e) etching-back a layer sequence deposited on the walls up to the wall protection; and

f) repeating b) to e) until the trench structure is filled.

2. The method of claim 1, wherein undercuts of the capacitor structure formed by e) are filled by dielectric material.

3. The method of claim 1, wherein deposition parameters during the anisotropic application of conductive and/or dielectric material, for the purpose of setting different layer thicknesses (d_m, d_i), are varied in accordance with a predetermined potential profile in the stacking direction of the layered capacitor.

4. The method of claim 1, wherein etching-back with protection of the layer stack already formed is interposed when overhangs of deposited material are formed at an entrance to the trench structure.

5. The method of claim 1, wherein a) includes oxidizing in an oxygen and/or water vapor atmosphere.

6. The method of claim 1, wherein a) includes performing chemical vapor deposition the isotropic nitriding of the walls of the trench structure.

7. The method of claim 1, wherein b) includes sputtering.

8. The method of claim 1, wherein b) includes a directional vapor deposition.

9. The method of claim 1, wherein b) includes a directional ion beam deposition from a plasma.

10. The method of claim 1, further comprising removing the protective layer via plasma incineration.

11. The method of claim 1, wherein a photolithography method is performed for a masked application of the protective layer.