Through-substrate vias with polymer fill and method of fabricating same

• US 8,187,972 B2
• Filed: 01/26/2011
• Issued: 05/29/2012
• Est. Priority Date: 07/01/2008
• Status: Active Grant

• Current Assignee: Teledyne Scientific & Imaging, LLC (Teledyne Technologies Incorporated)
• Original Assignee: Teledyne Scientific & Imaging, LLC (Teledyne Technologies Incorporated)
• Inventors: Stupar, Philip A., DeNatale, Jeffrey F., Borwick, Robert L. III, Papavasiliou, Alexandros P.
• Primary Examiner(s): Bryant, Kiesha
• Assistant Examiner(s): Payen, Marvin
• Application Number:
  US13/014,585
• Publication Number:
  US 20110121427A1
• Time in Patent Office: 489 Days
• Field of Search: 257/532, 438/386, 438/667
• US Class Current: 438/667
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2223/54426 for alignment
• CPC Class Codes: H01L 2223/54453 for use prior to dicing
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/12044 OLED

Abstract

An through-substrate via fabrication method requires forming a through-substrate via hole in a semiconductor substrate, depositing an electrically insulating, continuous and substantially conformal isolation material onto the substrate and interior walls of the via using ALD, depositing a conductive material into the via and over the isolation material using ALD such that it is electrically continuous across the length of the via hole, and depositing a polymer material over the conductive material such that any continuous top-to-bottom openings present in the via holes are filled by the polymer material. The basic fabrication method may be extended to provide vias with multiple conductive layers, such as coaxial and triaxial vias.

Claims

1. A process for fabricating one or more through-substrate vias in a first semiconductor substrate which may contain active circuitry, the first substrate having a first surface and a second surface, comprising:

forming one or more through-substrate via holes in a first semiconductor substrate;

depositing an isolation material directly onto the first substrate and onto the interior walls of each of said through-substrate via holes using atomic layer deposition (ALD) such that said isolation material is electrically insulating, continuous and substantially conformal;

depositing conductive material into each of said via holes over said isolation material using ALD such that said conductive material is electrically continuous across the length of each of said via holes;

depositing a polymer material over said conductive material such that any continuous top-to-bottom openings present in said via holes are filled by said polymer material;

patterning and dry etching said polymer and conductive materials such that said polymer material is confined to the interior of each of said via holes and said conductive material is confined to the interior of said via holes and the area immediately surrounding said via holes on said first and second surfaces of said first substrate such that said through-substrate vias are electrically isolated from each other; and

planarizing at least one of said first and second surfaces of said first substrate after said patterning and dry etching of said polymer and conductive materials to provide a planar surface suitable for photolithographic processing.

2. The process of claim 1, wherein each of said through-substrate via holes are formed by:

dry etching a first cavity into said first substrate'"'"'s first surface, said first cavity having a first diameter; and

dry etching a second cavity into said first substrate'"'"'s second surface, said second cavity having a second diameter, wherein the first and second cavities form a single continuous aperture through the first substrate.

3. The process of claim 1, wherein said polymer material is a member of the parylene family.

4. The process of claim 1, wherein said polymer material is vapor deposited.

5. The process of claim 1, further comprising performing additional processing steps on said planarized surfaces to form electrical interconnects to the conductive material within said vias.

6. The process of claim 1, further comprising:

providing a second semiconductor substrate which may contain active circuitry, the second substrate having a first surface and a second surface and arranged to be interconnected with said first substrate using said through-substrate vias in said first substrate and an interconnection means.

7. The process of claim 6, wherein said first and second substrates are stacked and said interconnection means is selected from a group comprising indium bumps, metal thermocompression bonds and solder bumps between said substrates.

8. The process of claim 6, further comprising:

forming one or more through-substrate via holes in said second substrate;

depositing an isolation material directly onto the second substrate and onto the interior walls of each of said through-substrate via holes using atomic layer deposition (ALD) such that said isolation material is electrically insulating, continuous and substantially conformal;

depositing conductive material into each of said via holes over said isolation material using ALD such that said conductive material is electrically continuous across the length of each of said via holes; and

depositing a polymer material over said conductive material such that any continuous top-to-bottom openings present in said via holes are filled by said polymer material.

9. The process of claim 1, further comprising:

depositing a second layer of isolation material over said conductive material such that said second layer of isolation material is electrically insulating, continuous and substantially conformal; and

depositing a second layer of conductive material over said second layer of isolation material such that said second layer of conductive material is electrically continuous across the length of said via hole;

such that said layers of isolation material and conductive material function as a capacitor.

10. The process of claim 1, further comprising:

depositing a second layer of isolation material over said conductive material such that said second layer of isolation material is electrically insulating, continuous and substantially conformal; and

depositing a second layer of conductive material over said second layer of isolation material such that said second layer of conductive material is electrically continuous across the length of said via hole;

such that said layers of isolation material and conductive material function as a coaxial via through said substrate.

11. The process of claim 10, further comprising:

depositing a third layer of isolation material over said second layer of conductive material such that said third layer of isolation material is electrically insulating, continuous and substantially conformal; and

depositing a third layer of conductive material over said second layer of isolation material such that said third layer of conductive material is electrically continuous across the length of said via hole;

such that said layers of isolation material and conductive material form a triaxial via through said substrate.

12. The process of claim 1, wherein said steps of forming the via holes, depositing the isolation material, depositing the conductive material and depositing the polymer material are performed at a temperature of <

300°

C.

13. The process of claim 1, further comprising preparing said isolation material by activating it with a seed layer which reacts with said conductive material.

14. The process of claim 1, wherein the conductive material is chosen from a group consisting of nickel, palladium, platinum, ruthenium, tungsten, iridium, copper, titanium nitride or zinc oxide.

15. The process of claim 1, wherein said deposition of an isolation material by ALD comprises deposition of inorganic oxides capable of providing electrical insulation and conformal surface coatings.

16. The process of claim 15, wherein said isolation material is chosen from a group of metal oxides comprising the oxides of aluminum, titanium, tantalum, niobium, zirconium, hafnium, lanthanum, yttrium, cerium, silicon, scandium, chromium, and erbium.

17. The process of claim 1, further comprising forming metallization on one or both of said first and second substrate surfaces to provide electrical connections to the conductive material layers of said through-substrate via.