Field effect transistor

• US 8,188,471 B2
• Filed: 08/29/2008
• Issued: 05/29/2012
• Est. Priority Date: 09/05/2007
• Status: Active Grant

• Current Assignee: Canon Kabushiki Kaisha (Canon Inc.)
• Original Assignee: Canon Kabushiki Kaisha (Canon Inc.)
• Inventors: Iwasaki, Tatsuya, Itagaki, Naho
• Primary Examiner(s): Tran, Tan N
• Application Number:
  US12/671,052
• Publication Number:
  US 20100258794A1
• Time in Patent Office: 1,369 Days
• Field of Search: 257/43, 257/57, 257/72, 257/E29.079
• US Class Current: 257/57
• CPC Class Codes: C23C 14/086 of zinc, germanium, cadmium, indium, tin, thallium or bismuth
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

A field effect transistor is provided including a gate electrode (for example, 15), a source electrode (13), a drain electrode (14) and a channel layer (11) to control current flowing between the source electrode (13) and the drain electrode (14) by applying a voltage to the gate electrode (15). The channel layer (11) is constituted of an amorphous oxide containing In and Si and having a compositional ratio expressed by Si/(In+Si) of not less than 0.05 and not more than 0.40.

Claims

1. A field effect transistor comprising:

a gate electrode;

a source electrode;

a drain electrode; and

a channel layer comprising an oxide material containing In and Si and having a compositional ratio expressed by Si/(In+Si) of not less than 0.05 and not more than 0.40.

2. The field effect transistor according to claim 1, wherein the compositional ratio expressed by Si/(In+Si) is not less than 0.15 and not more than 0.30.

3. The field effect transistor according to claim 1, wherein the compositional ratio expressed by Si/(In+Si) is not less than 0.15 and not more than 0.23.

8. The field effect transistor according to claim 1, wherein said oxide material is an amorphous oxide material.

4. A field effect transistor comprising:

a gate electrode;

a source electrode;

a drain electrode; and

a channel layer comprising an oxide material containing In, Zn and Si and having a compositional ratio of Si expressed by Si/(In+Zn+Si) of not less than 0.05 and not more than 0.40.

9. The field effect transistor according to claim 4, wherein said the oxide material is an amorphous oxide material.

5. A field effect transistor comprising:

a gate electrode;

a source electrode;

a drain electrode;

a channel layer; and

a gate insulating layer in contact with said channel layer,

wherein said channel layer comprises an oxide material containing In and Si and having a compositional ratio expressed by Si/(In+Si) of not less than 0.05 and not more than 0.40, and

wherein said gate insulating layer comprises of an oxide or nitride, containing Si.

6. The field effect transistor according to claim 5, wherein said gate insulating layer comprises a silicon oxide.

7. The field effect transistor according to claim 6, wherein said channel layer and the gate insulating layer are formed by a sputtering method.

10. The field effect transistor according to claim 5, wherein said oxide material is an amorphous oxide material.