Semiconductor device and manufacturing method thereof

• US 8,188,477 B2
• Filed: 11/17/2009
• Issued: 05/29/2012
• Est. Priority Date: 11/21/2008
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Miyairi, Hidekazu, Yamazaki, Shunpei, Osada, Takeshi
• Primary Examiner(s): Tran, Tan N
• Application Number:
  US12/620,009
• Publication Number:
  US 20100301326A1
• Time in Patent Office: 924 Days
• Field of Search: 257/59, 257/72, 257/258
• US Class Current: 257/59
• CPC Class Codes: G02F 1/1362 Active matrix addressed cells G02F1/134336, G02F1/134363 take precedence
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1251 comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/78645 with multiple gate
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H10K 59/1213 the pixel elements being TFTs
• CPC Class Codes: H10K 59/131 Interconnections, e.g. wiring lines or terminals

Abstract

As a display device has higher definition, the number of pixels is increased and thus, the number of gate lines and signal lines is increased. When the number of gate lines and signal lines is increased, it is difficult to mount IC chips including driver circuits for driving the gate lines and the signal lines by bonding or the like, whereby manufacturing cost is increased. A pixel portion and a driver circuit for driving the pixel portion are provided on the same substrate, and at least part of the driver circuit comprises a thin film transistor including an oxide semiconductor sandwiched between gate electrodes. A channel protective layer is provided between the oxide semiconductor and a gate electrode provided over the oxide semiconductor. The pixel portion and the driver circuit are provided on the same substrate, which leads to reduction of manufacturing cost.

Claims

1. A semiconductor device comprising:

a first gate electrode over an insulating surface;

a first insulating layer over the first gate electrode;

an oxide semiconductor layer comprising a channel formation region over the first insulating layer;

a channel protective layer over and in contact with the oxide semiconductor layer;

a source electrode and a drain electrode over the oxide semiconductor layer;

a second insulating layer covering the source electrode and the drain electrode; and

a second gate electrode over the second insulating layer;

wherein the second insulating layer is in direct contact with at least a portion of the channel protective layer, the portion being over the channel formation region.

2. The semiconductor device according to claim 1, wherein a width of the first gate electrode is larger than a width of the second gate electrode.

3. The semiconductor device according to claim 1, wherein a width of the first gate electrode is smaller than a width of the second gate electrode.

4. The semiconductor device according to claim 1, wherein a width of the first gate electrode is larger than a width of the channel protective layer, and a width of the second gate electrode is smaller than the width of the channel protective layer.

5. The semiconductor device according to claim 1, wherein the oxide semiconductor layer comprises at least one of indium, gallium, and zinc.

6. The semiconductor device according to claim 1, wherein a potential of the first gate electrode is the same as a potential of the second gate electrode.

7. The semiconductor device according to claim 1, wherein a potential of the first gate electrode is different from that of a potential of the second gate electrode.

8. The semiconductor device according to claim 1, wherein the portion of the channel protective layer is a central portion of the channel protective layer.

9. A semiconductor device comprising:

a first gate electrode over an insulating surface;

a first insulating layer over the first gate electrode;

an oxide semiconductor layer comprising a channel formation region over the first insulating layer;

a channel protective layer over and in contact with the oxide semiconductor layer;

a buffer layer over the oxide semiconductor layer and the channel protective layer;

a source electrode and a drain electrode over the buffer layer;

a second insulating layer covering the source electrode and the drain electrode; and

a second gate electrode over the second insulating layer;

wherein the second insulating layer is in direct contact with at least a portion of the channel protective layer, the portion being over the channel formation region.

10. The semiconductor device according to claim 9, wherein a width of the first gate electrode is larger than a width of the second gate electrode.

11. The semiconductor device according to claim 9, wherein a width of the first gate electrode is larger than a width of the channel protective layer, and a width of the second gate electrode is smaller than the width of the channel protective layer.

12. The semiconductor device according to claim 9, wherein the oxide semiconductor layer comprises at least one of indium, gallium, and zinc.

13. The semiconductor device according to claim 9, wherein a potential of the first gate electrode is the same as a potential of the second gate electrode.

14. The semiconductor device according to claim 9, wherein a potential of the first gate electrode is different from that of a potential of the second gate electrode.

15. The semiconductor device according to claim 9, wherein the portion of the channel protective layer is a central portion of the channel protective layer.