SiC semiconductor device with self-aligned contacts, integrated circuit and manufacturing method

• US 8,188,482 B2
• Filed: 12/22/2008
• Issued: 05/29/2012
• Est. Priority Date: 12/22/2008
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Treu, Michael, Rueschenschmidt, Kathrin, Haeberlen, Oliver, Auerbach, Franz
• Primary Examiner(s): Louie, Wai Sing
• Assistant Examiner(s): TANG, SUIAN
• Application Number:
  US12/341,370
• Publication Number:
  US 20100155743A1
• Time in Patent Office: 1,254 Days
• Field of Search: 257/77, 257/134, 257256-287, 257/E29.069, 257/E29.174, 257/E29.188, 257/341, 257/342, 438/186
• US Class Current: 257/77
• CPC Class Codes: H01L 29/1058 with PN junction gate
• CPC Class Codes: H01L 29/1066 Gate region of field-effect devices with PN junction gate
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/66901 with a PN homojunction gate
• CPC Class Codes: H01L 29/66909 Vertical transistors, e.g. tecnetrons
• CPC Class Codes: H01L 29/808 with a PN junction gate , e.g. PN homojunction gate H01L29/7725, H01L29/775, H01L29/778, H01L29/806 take precedence
• CPC Class Codes: H01L 29/8083 Vertical transistors SIT H01L29/7722

Abstract

One aspect includes a semiconductor device with self-aligned contacts, integrated circuit and manufacturing method. One embodiment provides gate control structures. Each of the gate control structures is configured to control the conductivity of a channel region within a silicon carbide substrate by field effect. A contact hole is self-aligned to opposing sidewalls of adjacent gate control structures by intermediate spacers.

Claims

1. A Junction Field Effect Transistor, comprising:

gate control structures each configured to control the conductivity of a channel region within a silicon carbide substrate by field effect; and

a contact being self-aligned to opposing sidewalls of adjacent gate control structures by intermediate spacers,

wherein the contact is connected to a bottom gate region of the Junction Field Effect Transistor and the gate control structures include top gate control structures, the channel region being sandwiched between one of the top gate structures and the bottom gate region, and

wherein a source region is embedded in the bottom gate region.

2. The Junction Field Effect Transistor of claim 1, wherein the contact has a same lateral distance to both adjacent gate control structures, respectively.

3. The Junction Field Effect Transistor of claim 1, wherein the bottom gate region is self-aligned to the source region.

4. A method for manufacturing the Junction Field Effect Transistor of claim 1, the method comprising:

forming the gate control structures, wherein each of the gate control structures is configured to control the conductivity of the channel region within the silicon carbide substrate by field effect;

forming the contact being self-aligned to opposing sidewalls of adjacent gate control structures by intermediate spacers;

wherein the gate control structures result from patterning a gate control structure layer via a hard mask; and

the spacers result from forming a spacer layer over the hard mask and removing the spacer layer until the spacers are left,

wherein the hard mask is patterned so as to leave a remnant portion of the hard mask at least over the gate control structures and an additional remnant portion of the hard mask in a peripheral area of an active cell region.

5. The method of claim 4, further comprising:

forming semiconductor regions within the silicon carbide substrate by ion implantation of impurities and annealing implant damages prior to formation of the gate control structures.

6. The method of claim 4, further comprising:

extending the contact into the silicon carbide substrate by forming a cavity within the silicon carbide substrate.

7. The method of claim 4, comprising forming the spacers by etching the spacer layer resulting in an at least partly curved spacer sidewall profile broadening the spacers with decreasing distance to a surface of the silicon carbide substrate.

8. The method of claim 6, comprising carrying out annealing of the implant damages with the blank SiC substrate having no oxide layers formed thereon.

9. A method of manufacturing the Junction Field Effect Transistor of claim 1 within the silicon carbide substrate, the method comprising:

forming the gate control structures, wherein each of the gate control structures is configured to control the conductivity of the channel region within the silicon carbide substrate by field effect;

wherein forming the gate control structure includes forming buried gate regions, channel regions and top gate regions, wherein at least one of the buried gate regions, the channel regions and the top gate regions is formed by ion implantation of impurities and subsequent annealing of implant damages; and

thereafter

forming intermediate spacers extending along sidewalls of the gate control structures and the contact being self-aligned to opposing sidewalls of adjacent gate control structures by the intermediate spacers.

10. The method of claim 9, further comprising carrying out the annealing of the implant damages with the blank SiC substrate having no oxide layers formed thereon.

11. The method of claim 9, further comprising forming the buried gate regions in self-aligned manner with regard to previously formed source regions.

12. The method of claim 9, wherein the gate control structures result from patterning a gate control structure layer via a hard mask;

and

the spacers result from forming a spacer layer over the hard mask and removing the spacer layer until the spacers are left.

13. The method of claim 12, further comprising forming the spacers by etching the spacer layer resulting in an at least partly curved spacer sidewall profile broadening the spacers with decreasing distance to a surface of the silicon carbide substrate.

14. The method of claim 9, further comprising:

patterning the hard mask so as to leave a remnant portion of the hard mask at least over the gate control structures.