Semiconductor device

• US 8,188,484 B2
• Filed: 12/24/2009
• Issued: 05/29/2012
• Est. Priority Date: 12/25/2008
• Status: Active Grant

• Current Assignee: ROHM Co., Ltd.
• Original Assignee: ROHM Co., Ltd.
• Inventors: Nakano, Yuki
• Primary Examiner(s): Tran, Minh-Loan T
• Assistant Examiner(s): Erdem, Fazli
• Application Number:
  US12/654,621
• Publication Number:
  US 20100193796A1
• Time in Patent Office: 887 Days
• Field of Search: 257/66, 257/77, 257/330, 257/E29.104, 257/E29.257, 257/E29.262, 257/E21.41
• US Class Current: 257/77
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7803 structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7805 in antiparallel, e.g. freewheel diode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The semiconductor device according to the present invention includes: a semiconductor layer made of SiC; an impurity region formed by doping the semiconductor layer with an impurity; and a contact wire formed on the semiconductor layer in contact with the impurity region, while the contact wire has a polysilicon layer in the portion in contact with the impurity region, and has a metal layer on the polysilicon layer.

Claims

1. A semiconductor device comprising:

a semiconductor layer made of SiC and having a surface;

an impurity region formed on a surface layer portion of the semiconductor layer by doping the semiconductor layer with an impurity, the impurity forming a part of the surface of the semiconductor layer; and

a contact wire formed on the surface of the semiconductor layer in contact with the impurity region, wherein

the contact wire has at least a polysilicon layer and a metal layer, and has a multilayer structure obtained by successively laminating the polysilicon layer and the metal layer such that the polysilicon layer is in contact with the impurity region.

2. The semiconductor device according to claim 1, further comprising:

a gate trench dug down from the surface of the semiconductor layer;

a first conductivity type body region formed in the semiconductor layer on a side portion of the gate trench;

a gate insulating film formed on the inner surface of the gate trench; and

a gate electrode embedded in the gate trench through the gate insulating film, wherein

the impurity region is a second conductivity type source region formed on a surface layer portion of the body region adjacently to the gate trench, and

the contact wire is a source wire in contact with the source region.

3. The semiconductor device according to claim 1, further comprising:

a first conductivity type body region formed on a surface layer portion of the semiconductor layer;

a gate insulating film formed on the surface of the semiconductor layer; and

a gate electrode formed on the gate insulating film and opposed to the body region through the gate insulating film, wherein

the impurity region is a second conductivity type source region formed on a surface layer portion of the body region, and

the contact wire is a source wire in contact with the source region.

4. The semiconductor device according to claim 1, wherein the polysilicon layer is a high-concentration doped layer doped with an impurity in a concentration of 10¹⁹ to 10²¹ cm⁻

3.

5. The semiconductor device according to claim 1, wherein a layer containing titanium is interposed between the polysilicon layer and the metal layer.

6. The semiconductor device according to claim 5, wherein

the metal layer has a layer containing Al, and

the layer containing titanium has a structure obtained by laminating a Ti layer and a TiN layer in this order from the side closer to the polysilicon layer.

7. The semiconductor device according to claim 1, wherein the polysilicon layer is doped with at least one type of conductive impurity selected from a group consisting of B, P, Al and N.