Semiconductor device and method of manufacturing semiconductor device

• US 8,188,538 B2
• Filed: 12/24/2009
• Issued: 05/29/2012
• Est. Priority Date: 12/25/2008
• Status: Active Grant

• Current Assignee: ROHM Co., Ltd.
• Original Assignee: ROHM Co., Ltd.
• Inventors: Nakano, Yuki, Nakamura, Ryota
• Primary Examiner(s): Tran, Minhloan T
• Assistant Examiner(s): Erdem, Fazli
• Application Number:
  US12/654,620
• Publication Number:
  US 20100193799A1
• Time in Patent Office: 887 Days
• Field of Search: 257/77, 257/330, 257/E29.104, 257/66, 257/331, 257/301, 257/E29.262, 257/E21.41, 257/194, 257/333, 438/589, 438/270
• US Class Current: 257/330
• CPC Class Codes: H01L 21/046 using ion implantation
• CPC Class Codes: H01L 21/0485 Ohmic electrodes
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7803 structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7805 in antiparallel, e.g. freewheel diode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

The semiconductor device according to the present invention includes: a semiconductor layer of a first conductivity type made of SiC having an Si surface; a gate trench dug down from the surface of the semiconductor layer; a gate insulating film formed on a bottom surface and a side surface of the gate trench so that the ratio of the thickness of a portion located on the bottom surface to the thickness of a portion located on the side surface is 0.3 to 1.0; and a gate electrode embedded in the gate trench through the gate insulating film.

Claims

1. A semiconductor device, comprising:

a semiconductor layer of a first conductivity type made of SiC having a first Si surface;

a gate trench dug down from the first Si surface of the semiconductor layer such that the gate trench has a bottom surface parallel to the first Si surface and a side surface orthogonal to the first Si surface, the bottom surface being a second Si surface;

a body region of a second conductivity type formed in the semiconductor layer and defining one part of the side surface of the gate trench;

a source region of the first conductivity type formed on a surface layer portion of the body region and defining another part of the side surface of the gate trench;

a drain region of the first conductivity type formed on an opposite side of the source region from the body region and defining the bottom surface of the gate trench;

a gate insulating film including an insulating film bottom portion formed on the bottom surface of the gate trench and an insulating film side portion formed on the side surface of the gate trench, the insulating film bottom portion and the insulating film side portion intersecting each other and having respective uniform thicknesses; and

a gate electrode embedded in the gate trench through the gate insulating film, wherein

the ratio of the thickness of the insulating film bottom portion to the thickness of the insulating film side portion is between 0.3 and 1.0.

2. The semiconductor device according to claim 1, further comprising an implantation layer formed by implantation of an impurity in a portion of the semiconductor layer reaching an intermediate portion of the semiconductor layer in a thickness direction from the bottom surface of the gate trench.

3. The semiconductor device according to claim 2, wherein the implantation layer is formed by implantation of an impurity of the second conductivity type.

4. The semiconductor device according to claim 1, wherein the thickness of the insulating film side portion is not more than 2000 Å

.

5. The semiconductor device according to claim 1, wherein an end portion of the bottom portion of the gate trench in a direction orthogonal to the gate width is bent outward.

6. The semiconductor device according to claim 1, wherein the first Si surface and the second Si surface are defined by a (0001) plane.

7. The semiconductor device according to claim 1, wherein

the gate insulating film contains nitrogen.

8. The semiconductor device according to claim 7, wherein the concentration of an impurity of the second conductivity type in the body region is not more than 10¹⁹ cm⁻

3.

9. The semiconductor device according to claim 7, further comprising a source wire formed on the semiconductor layer and in contact with the source region, wherein the source wire has a polysilicon layer in the portion in contact with the source region, and has a metal layer on the polysilicon layer.

10. The semiconductor device according to claim 9, wherein an intermediate layer containing Ti is interposed between the polysilicon layer and the metal layer.

11. The semiconductor device according to claim 10, wherein

the metal layer has a layer containing Al, and

the intermediate layer has a structure obtained by laminating a Ti layer and a TiN layer in this order from the side of the polysilicon layer.

12. A method of manufacturing a semiconductor device, comprising the steps of:

forming a gate trench on a surface layer portion of a semiconductor layer of a first conductivity type made of SiC having a first Si surface, the gate trench being dug down from the first Si surface of the semiconductor layer such that the gate trench has a bottom surface parallel to the first Si surface and a side surface orthogonal to the first Si surface, the bottom surface being a second Si surface;

forming a body region of a second conductivity type in the semiconductor layer to define one part of the side surface of the gate trench;

forming a source region of a first conductivity type on a surface layer portion of the body region to define another part of the side surface of the gate trench;

forming a drain region of a first conductivity type on an opposite side of the source region from the body region to define the bottom surface of the gate trench;

forming a gate insulating film including an insulating film bottom portion to be formed on the bottom surface and an insulating film side portion to be formed the side surface of the gate trench by oxidizing the bottom surface and the side surface of the gate trench in gas containing nitrogen and oxygen at a heat treatment temperature of not less than 1200°

C., the insulating film bottom portion and the insulating film side portion intersecting each other and having respective uniform thicknesses; and

forming a gate electrode on the gate insulating film to fill up the gate trench.

13. The method of manufacturing a semiconductor device according to claim 12, wherein the bottom surface and the side surface of the gate trench are oxidized in gas containing at least N₂O in the step of forming the gate insulating film.

14. The method of manufacturing a semiconductor device according to claim 13, wherein N₂O gas is fed at a flow rate of not more than 30% with respect to the total flow rate of fed gas in the step of forming the gate insulating film.

15. The method of manufacturing a semiconductor device according to claim 12, wherein the first Si surface and the second Si surface are defined by a (0001) plane.