Semiconductor integrated circuit

• US 8,188,568 B2
• Filed: 02/07/2011
• Issued: 05/29/2012
• Est. Priority Date: 04/20/2010
• Status: Active Grant

• Current Assignee: Godo Kaisha IP Bridge 1 (IP Bridge, Inc.)
• Original Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Inventors: Imahashi, Manabu
• Primary Examiner(s): Loke, Steven
• Assistant Examiner(s): HALL, VICTORIA KATHLEEN
• Application Number:
  US13/022,035
• Publication Number:
  US 20110254120A1
• Time in Patent Office: 477 Days
• Field of Search: 257/355, 257/358, 257361-363, 257/552, 257/593, 257/173, 257/526, 257/565, 257/587
• US Class Current: 257/526
• CPC Class Codes: H01L 27/0259 using bipolar transistors as protective elements
• CPC Class Codes: H01L 29/0821 Collector regions of bipolar transistors
• CPC Class Codes: H01L 29/732 Vertical transistors

Abstract

A semiconductor circuit includes: a first diffusion layer formed on a substrate; a second diffusion layer formed in an upper part of the first diffusion layer; a third diffusion layer formed in an upper part of the second diffusion layer; a fourth diffusion layer formed in the upper part of the first diffusion layer; and a fifth diffusion formed below the third diffusion layer. A sum of a shortest distance from the third diffusion layer to the fifth diffusion layer and a shortest distance from the fifth diffusion layer or the lower end of the first diffusion layer to the fourth diffusion layer is smaller than a shortest distance from the third diffusion layer to the fourth diffusion layer. The substrate, the second and the fifth diffusion layer are a first conductivity type and the others are a second conductivity type.

Claims

1. A semiconductor integrated circuit, comprising:

a semiconductor substrate of a first conductivity type;

a first diffusion layer of a second conductivity type formed on the semiconductor substrate or in an upper part of the semiconductor substrate;

a second diffusion layer of the first conductivity type formed in an upper part of the first diffusion layer, and serving as a base;

a third diffusion layer of the second conductivity type formed in an upper part of the second diffusion layer, and serving as an emitter;

a fourth diffusion layer of the second conductivity type formed in the upper part of the first diffusion layer so as to be separated from the second diffusion layer, and serving as a collector contact; and

a fifth diffusion layer of the first conductivity type formed at least below the third diffusion layer so as to be separated from the second diffusion layer in a depth direction, and so as to have a lower end located below a lower end of the first diffusion layer, wherein

a sum of a shortest distance from the third diffusion layer to the fifth diffusion layer and a shorter one of a shortest distance from the fifth diffusion layer to the fourth diffusion layer and a shortest distance from the lower end of the first diffusion layer to the fourth diffusion layer is smaller than a shortest distance from the third diffusion layer to the fourth diffusion layer.

2. The semiconductor integrated circuit of claim 1, wherein

the fifth diffusion layer is also formed below the fourth diffusion layer, and is not in contact with the fourth diffusion layer.

3. The semiconductor integrated circuit of claim 2, wherein

the fifth diffusion layer comprises two portions which are formed below the third diffusion layer and below the fourth diffusion layer, and these two portions of the fifth diffusion layer are separated from each other by the first diffusion layer.

4. The semiconductor integrated circuit of claim 1, further comprising:

an element isolation region formed around the first diffusion layer, and

the fifth diffusion layer is in contact with the element isolation region.

5. The semiconductor integrated circuit of claim 1, wherein

the fourth diffusion layer includes, below the collector contact, a region having a higher impurity concentration than the first diffusion layer.

6. The semiconductor integrated circuit of claim 1, wherein

a sixth diffusion layer serving as a base contact is formed on an opposite lateral side of the third diffusion layer from the fourth diffusion layer in the upper part of the second diffusion layer so as to be separated from the third diffusion layer, and

the sixth diffusion layer is of the first conductivity type, and has a higher impurity concentration than the second diffusion layer.

7. The semiconductor integrated circuit of claim 1, wherein

the second diffusion layer and the third diffusion layer are electrically connected to a lowest potential, and the fourth diffusion layer is electrically connected to an input/output terminal or a power supply terminal, and an internal circuit.

8. The semiconductor integrated circuit of claim 1, wherein

the first diffusion layer is formed on the semiconductor substrate by epitaxial growth.

9. The semiconductor integrated circuit of claim 1, wherein

an oxide film is formed between the second diffusion layer and the fourth diffusion layer.

10. The semiconductor integrated circuit of claim 1, wherein

the third diffusion layer and the fourth diffusion layer have a higher impurity concentration than the first diffusion layer.