Semiconductor device including leadframe having power bars and increased I/O
First Claim
1. A semiconductor package, comprising:
- a generally planar die pad defining multiple peripheral edge segments;
a plurality of first leads which are disposed in spaced relation to and at least partially circumvent the die pad;
a plurality of second leads which are disposed in spaced relation to and at least partially circumvent the die pad, at least some of the first leads being disposed between the die pad and the second leads; and
at least one power bar disposed in spaced relation to and extending between at least some of the first and second leads, the power bar partially but not fully circumventing the die pad.
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Accused Products
Abstract
In accordance with the present invention, there is provided a semiconductor package (e.g., a QFP package) including a uniquely configured leadframe sized and configured to maximize the available number of exposed leads in the semiconductor package. More particularly, the semiconductor package includes a generally planar die pad or die paddle defining multiple peripheral edge segments. In addition, the semiconductor package includes a plurality of leads. Some of these leads include bottom surface portions which, in the completed semiconductor package, are exposed and at least partially circumvent the die pad, with other leads including portions which protrude from respective side surfaces of a package body in the completed semiconductor package. The semiconductor package also includes one or more power bars and/or one or more ground rings which are integral portions of the original leadframe used to fabricate the same.
367 Citations
20 Claims
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1. A semiconductor package, comprising:
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a generally planar die pad defining multiple peripheral edge segments; a plurality of first leads which are disposed in spaced relation to and at least partially circumvent the die pad; a plurality of second leads which are disposed in spaced relation to and at least partially circumvent the die pad, at least some of the first leads being disposed between the die pad and the second leads; and at least one power bar disposed in spaced relation to and extending between at least some of the first and second leads, the power bar partially but not fully circumventing the die pad. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A semiconductor package, comprising:
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a generally planar die pad defining multiple peripheral edge segments; a plurality of first leads which are disposed in spaced relation to and at least partially circumvent the die pad; a plurality of second leads which are disposed in spaced relation to and at least partially circumvent the die pad, at least some of the first leads being disposed between the die pad and the second leads; and at least first and second primary power bars disposed in spaced relation to and extending between at least some of the first and second leads. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17, 18, 19)
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20. A semiconductor package, comprising:
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a die pad; a plurality of first leads which are disposed in spaced relation to and at least partially circumvent the die pad; a plurality of second leads which are disposed in spaced relation to and at least partially circumvent the die pad, at least some of the first leads being disposed between the die pad and the second leads; and at least one power bar disposed in spaced relation to and extending between at least some of the first and second leads; the die pad and the first leads residing on a first plane, the power bar residing on a second plane, and the second leads residing on a third plane, the first, second and third planes extending in spaced, generally parallel to each other, with the second plane being disposed between the first and third planes.
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Specification