Input/output package architectures

• US 8,188,594 B2
• Filed: 10/01/2009
• Issued: 05/29/2012
• Est. Priority Date: 09/29/2008
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Ganesan, Sanka, Aygun, Kemal, Ramaswamy, Chandrashekhar, Palmer, Eric, Braunisch, Henning
• Primary Examiner(s): Soward, Ida M
• Application Number:
  US12/587,175
• Publication Number:
  US 20100096743A1
• Time in Patent Office: 971 Days
• Field of Search: 257/675, 257706-707, 257712-713, 257/796, 257/E23.051, 257/E23.101, 257/E23.105, 257/688, 257/690, 257/698
• US Class Current: 257/713
• CPC Class Codes: H01L 2223/6627 Waveguides, e.g. microstrip line, strip line, coplanar line
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 23/34 Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements thermal treatment apparatus H01L21/00
• CPC Class Codes: H01L 23/367 Cooling facilitated by shape of device H01L23/38, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence
• CPC Class Codes: H01L 23/498 Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers shape of the substrate H01L23/13
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49833 the chip support structure consisting of a plurality of insulating substrates
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 2924/00011 Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/15192 Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/19032 being a microstrip line type

Abstract

A high-speed I/O trace is part of an I/O package architecture for an integrated circuit package substrate. The integrated circuit package substrate includes an integrated heat spreader footprint on a die-side and the I/O trace to couple with an IC device to be disposed inside the IHS footprint. The I/O trace includes a pin-out terminal outside the IHS footprint to couple to an IC device to be disposed outside the IHS footprint. The high-speed I/O trace can sustain a data flow rate from a processor in a range from 5 gigabits per second (Gb/s) to 40 Gb/s.

Claims

1. An input/output (I/O) package architecture for an integrated circuit package substrate, comprising:

an integrated circuit (IC) package substrate including an integrated heat spreader (IHS) footprint on a die-side thereof; and

an I/O trace to couple with an IC device to be disposed inside the IHS footprint, wherein the I/O trace includes a pin-out terminal outside the IHS footprint to couple to an IC device to be disposed outside the IHS footprint, wherein the I/O trace is capable of transmitting data between an IC device to be mounted inside the IHS footprint and an IC device to be located outside the IHS footprint at a signal rate between 5 Gb/s and 40 Gb/s.

2. The I/O architecture of claim 1, wherein the pin-out terminal is disposed on the IC package substrate die side.

3. The I/O architecture of claim 1, wherein the I/O trace is an integral metal line.

4. The I/O architecture of claim 1, wherein the pin-out terminal is a detachable connector terminal for a flexible signal-transmission cable, wherein the pin-out terminal is disposed on the IC package substrate die side, and wherein the I/O trace is an integral metal line.

5. An input/output (I/O) package architecture for an integrated circuit package substrate, comprising:

an integrated circuit (IC) package substrate including an integrated heat spreader (IHS) footprint on a die-side thereof; and

an I/O trace to couple with an IC device to be disposed inside the IHS footprint, wherein the I/O trace includes a pin-out terminal outside the IHS footprint to couple to an IC device to be disposed outside the IHS footprint, wherein the pin-out terminal is a detachable connector terminal for a flexible signal-transmission cable.

6. An input/output (I/O) package architecture for an integrated circuit package substrate, comprising:

an integrated circuit (IC) package substrate including an integrated heat spreader (IHS) footprint on a die-side thereof; and

an I/O trace to couple with an IC device to be disposed inside the IHS footprint, wherein the I/O trace includes a pin-out terminal outside the IHS footprint to couple to an IC device to be disposed outside the IHS footprint, wherein the I/O trace includes a shielded stripline.

7. An input/output (I/O) package architecture for an integrated circuit package substrate, comprising:

an integrated circuit (IC) package substrate including an integrated heat spreader (IHS) footprint on a die-side thereof; and

an I/O trace to couple with an IC device to be disposed inside the IHS footprint, wherein the I/O trace includes a pin-out terminal outside the IHS footprint to couple to an IC device to be disposed outside the IHS footprint, wherein the I/O trace includes a microstrip disposed on the IC device package substrate die side.

8. An input/output (I/O) package architecture for an integrated circuit package substrate, comprising:

an integrated circuit (IC) package substrate including an integrated heat spreader (IHS) footprint on a die-side thereof;

an I/O trace to couple with an IC device to be disposed inside the IHS footprint, wherein the I/O trace includes a pin-out terminal outside the IHS footprint to couple to an IC device to be disposed outside the IHS footprint, wherein the I/O trace is an I/O first trace, and wherein the pin-out terminal is a pin-out first terminal; and

an I/O second trace to couple the IC device to be disposed inside the IHS footprint; and

a pin-out second terminal outside the IHS footprint to couple to an IC device to be located outside the IHS footprint, and wherein the pin-out first terminal and the pin-out second terminal are disposed parallel to an edge of the processor mounting substrate.

9. An input/output (I/O) package architecture for an integrated circuit package substrate, comprising:

an integrated circuit (IC) package substrate including an integrated heat spreader (IHS) footprint on a die-side thereof; and

an I/O trace to couple with an IC device to be disposed inside the IHS footprint, wherein the I/O trace includes a pin-out terminal outside the IHS footprint to couple to an IC device to be disposed outside the IHS footprint, wherein the pin-out terminal is part of a first terminal array, and wherein the first terminal array is configured along an edge of the IC package substrate.

10. An input/output (I/O) package architecture for an integrated circuit package substrate, comprising:

an integrated circuit (IC) package substrate including an integrated heat spreader (IHS) footprint on a die-side thereof; and

an I/O trace to couple with an IC device to be disposed inside the IHS footprint, wherein the I/O trace includes a pin-out terminal outside the IHS footprint to couple to an IC device to be disposed outside the IHS footprint, wherein the pin-out terminal is part of a first terminal array, and wherein the first terminal array has a pin-out terminal layout selected from square pitch, staggered pitch, hexagonal pitch, and face-centered pitch.

11. An input/output (I/O) package architecture for an integrated circuit package substrate, comprising:

an integrated circuit (IC) package substrate including an integrated heat spreader (IHS) footprint on a die-side thereof;

an I/O trace to couple with an IC device to be disposed inside the IHS footprint, wherein the I/O trace includes a pin-out terminal outside the IHS footprint to couple to an IC device to be disposed outside the IHS footprint, wherein the pin-out terminal is part of a first terminal array, wherein the first terminal array is configured along an edge of the IC package substrate; and

a second terminal array disposed along a second edge of the IC package substrate.

12. An input/output (I/O) package architecture for an integrated circuit package substrate, comprising:

an integrated circuit (IC) package substrate including an integrated heat spreader (IHS) footprint on a die-side thereof;

an I/O trace to couple with an IC device to be disposed inside the IHS footprint, wherein the I/O trace includes a pin-out terminal outside the IHS footprint to couple to an IC device to be disposed outside the IHS footprint, wherein the pin-out terminal is part of a first terminal array, wherein the first terminal array is configured along an edge of the IC package substrate; and

a second terminal array disposed along a second edge of the IC package substrate, and wherein the first terminal array and the second terminal array are disposed at parallel edges of the IC package substrate.

13. An input/output (I/O) package architecture for an integrated circuit package substrate, comprising:

an integrated circuit (IC) package substrate including an integrated heat spreader (IHS) footprint on a die-side thereof;

an I/O trace to couple with an IC device to be disposed inside the IHS footprint, wherein the I/O trace includes a pin-out terminal outside the IHS footprint to couple to an IC device to be disposed outside the IHS footprint, wherein the pin-out terminal is part of a first terminal array, wherein the first terminal array is configured along an edge of the IC package substrate; and

a second terminal array disposed along a second edge of the IC package substrate, and wherein the first terminal array and the second terminal array are disposed at orthogonal adjacent edges of the IC package substrate.

14. An input/output (I/O) package architecture for an integrated circuit package substrate, comprising:

an integrated circuit (IC) package substrate including an integrated heat spreader (IHS) footprint on a die-side thereof;

an I/O trace to couple with an IC device to be disposed inside the IHS footprint, wherein the I/O trace includes a pin-out terminal outside the IHS footprint to couple to an IC device to be disposed outside the IHS footprint, wherein the pin-out terminal is part of a first array of pin-out terminals, wherein the first array is configured along an edge of the IC device substrate; and

a second array disposed along a second edge of the IC device substrate; and

a third array disposed along a third edge of the IC device substrate.

15. An input/output (I/O) package architecture for an integrated circuit package substrate, comprising:

an integrated circuit (IC) package substrate including an integrated heat spreader (IHS) footprint on a die-side thereof;

an I/O trace to couple with an IC device to be disposed inside the IHS footprint, wherein the I/O trace includes a pin-out terminal outside the IHS footprint to couple to an IC device to be disposed outside the IHS footprint, wherein the pin-out terminal is part of a first terminal array, wherein the first terminal array is configured along an edge of the IC package substrate

a second terminal array disposed along a second edge of the IC package substrate;

a third terminal array disposed along a third edge of the IC package substrate; and

a fourth terminal array disposed along a fourth edge of the IC package substrate.

16. An input/output (I/O) package architecture package comprising:

an integrated circuit (IC) package substrate including an integrated heat spreader (IHS) footprint on a die-side thereof, and an IC device landing zone disposed within the IHS footprint;

an IC device disposed inside the IHS footprint;

an I/O trace coupled with the IC device, wherein the I/O trace is capable of transmitting data between the IC device and an IC device to be located outside the IHS footprint at a rate between 5 Gb/s and 40 Gb/s; and

wherein the I/O trace is an integral metal line, wherein the I/O trace includes a pin-out terminal outside the IHS footprint, wherein the pin-out terminal is disposed on the IC package substrate die side, and wherein the pin-out terminal is a detachable connector terminal for a flexible signal-transmission cable.

17. The package of claim 16, wherein the IC device is a processor, the package further including:

a flexible signal-transmission cable coupled to the pin-out terminal at a first end thereof; and

an IC second device coupled to the flexible signal-transmission cable at a second end thereof.

18. The package of claim 16, wherein the IC device is a processor, the package further including:

a flexible signal-transmission cable coupled to the pin-out terminal at a first end thereof;

an IC second device coupled to the flexible signal-transmission cable at a second end thereof; and

wherein the IC package substrate includes a terminal array located between a terminal array inner perimeter that corresponds to an edge of the IHS footprint, and a terminal array outer perimeter that corresponds to the IC package substrate at an edge thereof.

19. The package of claim 16, wherein the IC device is a processor, the package further including:

a flexible signal-transmission cable coupled to the pin-out terminal at a first end thereof;

an IC second device coupled to the flexible signal-transmission cable at a second end thereof; and

wherein the IC package substrate includes a terminal array located between a terminal array inner perimeter that corresponds to an edge of the IHS footprint, and a terminal array outer perimeter that corresponds to the IC package substrate at an edge thereof, and wherein the terminal array includes pin-out terminals between 120 and 400 in number.

20. The package of claim 16, wherein the IC device is a processor, the package further including:

a flexible signal-transmission cable coupled to the pin-out terminal at a first end thereof;

an IC second device coupled to the flexible signal-transmission cable at a second end thereof; and

wherein the IC package substrate includes a terminal array located between a terminal array inner perimeter that corresponds to an edge of the IHS footprint, and a terminal array outer perimeter that corresponds to the IC package substrate at an edge thereof, and wherein the terminal array occupies a first edge of the IC package substrate and a second edge of the IC package substrate.

21. A computing system comprising:

an integrated circuit (IC) package substrate including an integrated heat spreader (IHS) footprint on a die-side thereof, and an IC device landing zone disposed within the IHS footprint;

an IC first device disposed inside the IHS footprint;

an I/O trace coupled with the IC device, wherein the I/O trace is capable of transmitting data between the IC device and an IC second device to be located outside the IHS footprint at a rate between 5 Gb/s and 40 Gb/s;

wherein the I/O trace is an integral metal line, wherein the I/O trace includes a pin-out terminal outside the IHS footprint, wherein the pin-out terminal is disposed on the IC package substrate die side, and wherein the pin-out terminal is a detachable connector terminal for a flexible signal-transmission cable, and wherein the IC second device is one of a processor and external memory.

22. The computing system of claim 21, wherein the computing system is part of one of a cellular telephone, a pager, a portable computer, a desktop computer, and a two-way radio.