Semiconductor device, its manufacturing method, and sputtering target material for use in the method

• US 8,188,599 B2
• Filed: 02/27/2007
• Issued: 05/29/2012
• Est. Priority Date: 02/28/2006
• Status: Active Grant

• Current Assignee: JX Nippon Mining & Metals Corporation (ENEOS Holdings, Inc.)
• Original Assignee: Advanced Interconnect Materials, LLC
• Inventors: Koike, Junichi
• Primary Examiner(s): Loke, Steven
• Assistant Examiner(s): TAYLOR, EARL N
• Application Number:
  US11/912,393
• Publication Number:
  US 20090212432A1
• Time in Patent Office: 1,918 Days
• Field of Search: 257/751, 257/762, 257/E21.021, 257/E21.584
• US Class Current: 257/751
• CPC Class Codes: C23C 14/027 Graded interfaces
• CPC Class Codes: C23C 14/046 Coating cavities or hollow spaces, e.g. interior of tubes; Infiltration of porous substrates
• CPC Class Codes: C23C 14/08 Oxides C23C14/10 takes precedence
• CPC Class Codes: C23C 14/3414 Metallurgical or chemical aspects of target preparation, e.g. casting, powder metallurgy
• CPC Class Codes: C23C 14/5806 Thermal treatment
• CPC Class Codes: H01L 21/2855 by physical means, e.g. sputtering, evaporation H01L21/28518 - H01L21/28537 and H01L21/28568 take precedence
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76846 Layer combinations
• CPC Class Codes: H01L 21/76864 Thermal treatment
• CPC Class Codes: H01L 21/76873 for electroplating
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/12044 OLED

Abstract

A semiconductor device enables a barrier layer to fully acquire a barriering property against the diffusion of Cu from a wiring main body and the diffusion of Si from an insulating film, enhances the adhesiveness of the barrier layer and the insulating film and excels in reliability of operation over a long period of time. In this invention, a semiconductor device 1 provided on an insulating film 3 with a wiring includes the insulating film 3 containing silicon (Si), a wiring main body 8 formed of copper (Cu) in a groove-like opening 4 disposed in the insulating film 3, and a barrier layer 7 formed between the wiring main body 8 and the insulating film 3 and made of an oxide containing Cu and Si and Mn in such a manner that the atomic concentration of Cu decreases monotonously from the wiring main body 8 side toward the insulating film 3 side, the atomic concentration of Si decreases monotonously from the insulating film 3 side toward the wiring main body 8 side, and the atomic concentration of Mn is maximized in the region in which the atomic concentration of Cu and the atomic concentration of Si are approximately equal.

Claims

1. A semiconductor device comprising:

an insulating film including silicon (Si);

an interconnection located in a groove disposed on the insulating film the interconnection including copper (Cu); and

a barrier layer located between the insulating film and the interconnection, the barrier layer including a manganese (Mn)-based oxide having an atomic concentration of manganese (Mn) maximized in a central part of the barrier layer.

3. The semiconductor device of claim 1, wherein the insulating film includes silicon dioxide (SiO₂).

4. The semiconductor device of claim 1, wherein the insulating film includes silicon oxide nitride.

5. The semiconductor device of claim 1, wherein the insulating film includes silicon oxide fluoride.

6. The semiconductor device of claim 1, wherein the insulating film includes silicon oxide carbide.

7. The semiconductor device of claim 1, wherein the insulating film is located on an electroconductive silicon semiconductor film on a silicon substrate.

8. The semiconductor device of claim 1, wherein the interconnection has a manganese (Mn) ion in a side contiguous to the barrier layer, a valence of the manganese (Mn) ion being divalent or trivalent.

9. The semiconductor device of claim 1, wherein electric resistivity of the interconnection is substantially the same as that of a pure copper (Cu) interconnection located in a groove of the same shape.

10. The semiconductor device of claim 1, wherein the barrier layer includes copper (Cu).

11. The semiconductor device of claim 10, wherein the barrier layer has atomic concentration of copper (Cu) decreasing monotonically from the interconnection side toward the insulating film side.

12. The semiconductor device of claim 10, wherein the barrier layer has atomic concentration of copper (Cu) decreasing from the interconnection side toward the insulating film side with a plus or minus sign of a slope of the decrease not changed.

13. The semiconductor device of claim 10, wherein atomic concentration of copper (Cu) in the barrier layer is not more than the atomic concentration of manganese (Mn) in a central part of a thickness of the barrier layer.

15. The semiconductor device of claim 1, wherein the barrier layer has a thickness of not less than 1 nm, not more than ⅕

of a width of the groove, and not more than 10 nm.

16. The semiconductor device of claim 1, wherein the barrier layer is amorphous.

17. The semiconductor device of claim 1, wherein the barrier layer is located between electric fields formed at the interconnection side and the insulating film side.

20. The semiconductor device of claim 1, wherein maximum atomic concentration of manganese (Mn) is not less than 30 atom %.

24. The semiconductor device of claim 1, wherein the groove has an opening width of 90 nm t 5 nm, and the barrier layer has a thickness of 5 nm to 10 nm.

25. The semiconductor device of claim 1, wherein the groove has an opening width of 65 nm±

3 nm, and the barrier layer has a thickness of 7 nm±

3 nm.

26. The semiconductor device of claim 1, wherein the groove has an opening width of 45 nm±

2 nm, and the barrier layer has a thickness of 5 nm±

2 nm.

27. The semiconductor device of claim 1, wherein the groove has an opening width of 32 nm±

2 nm, and the barrier layer has a thickness of 3.5 nm±

1 nm.

28. The semiconductor device of claim 1, wherein the insulating film includes silicon dioxide (SiO₂) and has a thickness of 150 nm, the groove has an opening width of 90 nm, the barrier layer has a thickness of approximately 5 nm, and the interconnection has electric resistivity of approximately 2.5 μ

Ω

cm.

29. The semiconductor device of claim 28, wherein the barrier layer has atomic concentration of copper (Cu) decreasing monotonically from the interconnection side toward the insulating film side, the barrier layer has atomic concentration of silicon (Si) decreasing monotonically from the insulating film side toward the interconnection side, and manganese (Mn) atoms are concentrically accumulated with the atomic concentration of manganese (Mn) maximized in a region in which the atomic concentration of copper (Cu) and the atomic concentration of silicon (Si) are almost the same.

2. A semiconductor device comprising:

an insulating film including silicon (Si);

an interconnection located in a groove disposed on the insulating film, the interconnection including copper (Cu); and

a barrier layer located between the insulating film and the interconnection, the barrier layer containing an oxide including copper (Cu), silicon (Si) and manganese (Mn);

wherein the barrier layer is formed by an oxide including copper (Cu), silicon (Si) and manganese (Mn), the barrier layer having atomic concentration of copper (Cu) decreasing from the interconnection side toward the insulating film side, atomic concentration of silicon (Si) decreasing from the insulating film side toward the interconnection side, and atomic concentration of manganese (Mn) maximized in a region in which the atomic concentration of copper (Cu) and the atomic concentration of silicon (Si) are almost the same.

14. The semiconductor device of claim 2, wherein the atomic concentration of manganese (Mn) in a region of the barrier layer, in which the atomic concentration of copper (Cu) and the atomic concentration of silicon (Si) are substantially the same, is not less than twice the atomic concentration of copper (Cu) or silicon (Si).

18. The semiconductor device of claim 2, wherein the atomic concentration of copper (Cu) decreases from not less than 70 atom % to not more than 10 atom %.

19. The semiconductor device of claim 2, wherein the atomic concentration of silicon (Si) decreases from not less than 30 atom % to not more than 10 atom %.

21. The semiconductor device of claim 2, wherein a silicon (Si) atom exists both in the insulating film and in the barrier layer adjacent to their interface.

22. The semiconductor device of claim 2, wherein a copper (Cu) atom exists both in the insulating film and in the barrier layer adjacent to their interface.

23. The semiconductor device of claim 14, wherein the atomic concentration of manganese (Mn) in a region of the barrier layer, in which the atomic concentration of copper (Cu) and the atomic concentration of silicon (Si) are both less than 15 atom %, is more than 33 atom %.