Memory device having staggered memory operations

• US 8,190,808 B2
• Filed: 08/17/2004
• Issued: 05/29/2012
• Est. Priority Date: 08/17/2004
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Lai, Lawrence, Richardson, Wayne S., Bellows, Chad A.
• Primary Examiner(s): Peugh, Brian
• Assistant Examiner(s): Thammavong, Prasith
• Application Number:
  US10/920,508
• Publication Number:
  US 20060039227A1
• Time in Patent Office: 2,842 Days
• Field of Search: 711/5, 711/169
• US Class Current: 711/5
• CPC Class Codes: G11C 2207/2227 Standby or low power modes
• CPC Class Codes: G11C 7/1042 using interleaving techniques, i.e. read-write of one part of the memory while preparing another part
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

A memory system includes logical banks divided into sub-banks or collections of sub-banks. The memory system responds to memory-access requests (e.g., read and write) directed to a given logical bank by sequentially accessing sub-banks or collections of sub-banks. Sequential access reduces the impact of power-supply spikes induced by memory operations, and thus facilitates improved system performance. Some embodiments of the memory system combine sequential sub-bank access with other performance-enhancing features, such as wider power buses or increased bypass capacitance, to further enhance performance.

Claims

1. An integrated circuit, comprising:

first, second, third and fourth storage arrays, arranged in respective quadrants of the integrated circuit, the first and fourth storage arrays in diagonally-opposite quadrants and the second and third storage arrays in diagonally-opposite quadrants, each storage array serviced by a row decoder and a column decoder;

a controller to provide in response to a single activation request (a) row access signals to the row decoder for the first storage array and to the row decoder for the fourth storage array, and (b) subsequently, to provide row access signals to the row decoder for the second storage array and to the row decoder for the third storage array, and to, subsequent to providing the row access signals, to provide in response to a single read request, column access signals to the column decoder for the first storage array and to the column decoder for the fourth storage array, and subsequently, (d) column access signals to the column decoder for the second storage array and to the column decoder for the third storage array; and

a serializer to receive, corresponding to the row activation request and read request, first parallel data from the first and fourth storage arrays, and second parallel data from the third and second storage arrays, and to combine the first and second parallel data into a series of data for serial transmission.

2. The integrated circuit of claim 1, embodied as a dynamic random access memory (DRAM) integrated circuit, each of the first and second arrays comprising DRAM cells.

3. The integrated circuit of claim 2, where the controller issues precharge signals to the first and fourth arrays, and subsequently, issues precharge signals to the second and third arrays in response to a single precharge request.

4. The integrated circuit of claim 1, where the controller is to provide the row access signals for the first and fourth storage arrays at a first clock cycle, the row access signals for the second and third storage arrays at a second clock cycle, the column access signals for the first and fourth storage arrays at a third clock cycle, and the column access signals for the second and third column storage arrays at a fourth clock cycle.

5. The integrated circuit of claim 1, further comprising a first multiplexer to multiplex data transferred between the serializer and the first and third arrays, and a second multiplexer to multiplex data transferred between the serializer and the second and fourth arrays.

6. The integrated circuit of claim 1, further comprising a deserializer to separate serial input data into first, second, third and fourth write data, the first write data to be written to the first storage array, the second write data to be written to the second storage array, the third write data to be written to the third storage array and the fourth write data to be written to the fourth storage array.

7. The integrated circuit of claim 1, further comprising a memory request interface to receive memory-access requests from a memory controller integrated circuit.

8. The integrated circuit of claim 1, where the controller includes circuitry to issue read and write control signals to the first, second, third and fourth storage arrays.

9. The integrated circuit of claim 8, where the read and write control signals include column selection signals.

10. The integrated circuit of claim 1, where the integrated circuit utilizes a reference clock and where the integrated circuit is to output data in response to a read request at double data rate relative to the reference clock.

11. The integrated circuit of claim 1, where:

the integrated circuit comprises logical banks, each logical bank having an associated sub-bank in each of the four storage arrays;

the controller is, for access to any given logical bank, to sequentially provide respective row access signals to the row decoder for the associated sub-bank in the first storage array and to the row decoder for the associated sub-bank in the second storage array, and to sequentially provide respective row access signals to the row decoder for the associated sub-bank in the fourth storage array and to the row decoder for the associated sub-bank in the third storage array, from a single row activation request, and to, subsequent to providing the row access signals, to sequentially provide respective column access signals to the column decoder for the associated sub-bank in the first storage array and to the column decoder for the associated sub-bank in the second storage array, and to sequentially provide respective column access signals to the column decoder for associated sub-bank for the fourth storage array and to the column decoder for associated sub-bank in the third storage array, in response to a single read request; and

the serializer is to receive, corresponding to the row activation request and read request for the given logical bank, first parallel data from the associated sub-banks in the first and fourth storage arrays, and second parallel data from the associated sub-banks in the third and second storage arrays, and to combine the first and second parallel data into a series of data for serial transmission.

12. The integrated circuit of claim 11, where the logical banks number no less than four.

13. The integrated circuit of claim 11, where the logical banks number no less than sixteen.

14. The integrated circuit of claim 1, where the controller is to offset the respective row access signals to the row decoder for the first storage array and to the row decoder for the second storage array by an amount of time, and where the controller is to offset the respective row access signals to the row decoder for the fourth storage array and to the row decoder for the third storage array by an amount of time.

15. The integrated circuit of claim 14, where the amount of time used by the controller to offset the respective row access signals to the row decoder for the first storage array and to the row decoder for the second storage array is equal to one cycle of a reference clock for the integrated circuit, and where the amount of time used by the controller to offset the respective row access signals to the row decoder for the fourth storage array and to the row decoder for the third storage array is equal to one cycle of a reference clock for the integrated circuit.

16. A memory circuit, comprising:

a first logical memory bank divided into a plurality of arrays, including a first array, a second array, a third array and a fourth array, the first and fourth arrays physically-separated into diagonally-opposite quadrants of a memory core, and the second and third arrays physically-separated into diagonally-opposite quadrants of the memory core;

means for initiating activation, in response to a memory activation request having an associated row address, to (a) a first row in the first array and to a fourth row in the fourth array, and subsequently, to (b) a second row in the second array and to a third row in the third array;

means for initiating access, subsequent to sequentially initiating activation of the first, second, third and fourth rows and in response to a memory access request having an associated column address, to (a) first data in a first column of the first row and fourth data in a fourth column of the fourth row, and subsequently, to (b) second data in a second column of the second row and third data in a third column of the third row; and

means for converting the first, second, third and fourth data between a parallel format and a serial format, the means for converting to respectively exchange the first, second, third and fourth data (a) in parallel format with the respective arrays and (b) in a serial format with a data signaling path.

17. The memory circuit of claim 16, further comprising a first multiplexer to route data between the means for converting and a selective one of the first array or the third array, and a second multiplexer to route data between the means for converting and a selective one of the second array or the fourth array.

18. The memory circuit of claim 16, where the memory access request is a read request.

19. The memory circuit of claim 16, where the memory access request is a write request.

20. The memory circuit of claim 16, embodied as a dynamic random access memory in a multi-chip package.

21. The memory circuit of claim 16, further comprising means for sequentially precharging the first and second arrays subsequent to the memory access request.

22. An integrated circuit, comprising:

first, second, third, and fourth memory arrays presented as a single logical memory space arranged into respective physically-separated quadrants of the integrated circuit, the first and fourth memory arrays arranged in diagonally-opposite quadrants, and the second and third memory arrays arranged in diagonally-opposite quadrants;

first row decoder resources to service the first and fourth memory arrays, and second row decoder resources to service the second and third memory arrays;

first column decoder resources to service the first and fourth memory arrays, and second column decoder resources to service the second and third memory arrays;

a controller to retrieve data from each of the memory arrays responsive to a common memory read transaction, using row access signals provided to the respective row decoder resources, and subsequently, using column access signals provided to the respective column decoder resources; and

a serializer to load data in parallel from the first and fourth memory arrays, and subsequently, to load data in parallel from the second and third memory arrays, for serial transmission of data corresponding to the common memory read transaction from all four memory arrays as part of an uninterrupted series of data.

23. The integrated circuit of claim 22, further comprising:

a first multiplexer to supply data to the serializer from a selective one of the first or third memory arrays; and

a second multiplexer to supply data to the serializer from a selective one of the second or fourth memory arrays.

24. The integrated circuit of claim 23, further comprising a read pipe and a write pipe coupled to the first and second multiplexers to perform serial-parallel conversion and to exchange data in parallel with two of the four memory arrays at a time.

25. The integrated circuit of claim 24, where the controller issues precharge signals, subsequent to the column access signals, to the first and fourth memory arrays and then subsequently, to the second and third memory arrays.

26. A method of reading data from an integrated-circuit memory having first, second, third and fourth memory arrays, arranged in physically-separated quadrants of the integrated-circuit memory, the first and fourth memory arrays arranged in diagonally-opposite quadrants and the second and third memory arrays arranged as diagonally-opposite quadrants, the method comprising:

issuing row activation signals to the first and fourth memory arrays, and subsequent to issuing row activation signals to the first and fourth memory arrays, issuing row activation signals to the second and third memory arrays, to activate respective rows;

issuing, subsequent to issuing the row activation signals and in response to a read request, column access signals to the first and fourth memory arrays and, subsequent to issuing the column access signals to the first and fourth memory arrays, issuing column access signals to the second and third memory arrays, to read data from respective columns;

outputting a series of data, where the series includes data read from each of memory arrays in response to the read request.

27. The method of claim 26, further comprising issuing, subsequent to issuing the column access signals, precharge signals to the first and fourth memory arrays, and subsequent to issuing the precharge signals to the first and fourth memory arrays, issuing precharge signals to the second and third memory arrays.

28. A memory apparatus, comprising:

four memory arrays serviced by respective row decoders and by respective column decoders, each of the four memory arrays arranged into a respective physically separated quadrant of the memory apparatus;

an access controller to receive a single activation request and, responsive to the activation request, to transmit row access commands to a first pair of the memory arrays in diagonally-opposite quadrants and, subsequently, row access commands to a second pair of the memory arrays in the other diagonally-opposite quadrants, the access controller further to receive a single read request and, responsive to the read request, to transmit, subsequent to the row access commands, staggered column access commands to column decoders for the respective pairs of memory arrays; and

circuitry to combine data obtained from each of the memory arrays in response to the single read request into a series of data and to serially output the series of data.

29. The memory apparatus of claim 28, further comprising multiple logical banks, each having an associated sub-bank in a respective one of the four memory arrays, where the circuitry is adapted to combine a set of parallel data for a given logical bank from each associated sub-bank from the four memory arrays into a single series of data.