System and method for optimizing interconnections of memory devices in a multichip module

• US 8,190,819 B2
• Filed: 11/05/2010
• Issued: 05/29/2012
• Est. Priority Date: 08/29/2002
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Ryan, Kevin J.
• Primary Examiner(s): TSAI, SHENG JEN
• Application Number:
  US12/940,515
• Publication Number:
  US 20110055478A1
• Time in Patent Office: 571 Days
• Field of Search: 711/115, 711/E12.001
• US Class Current: 711/115
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay

Abstract

An apparatus and method couples memory devices in a memory module to a memory hub on the module such that signals traveling from the hub to the devices have the same propagation time regardless of which device is involved. The hub receives memory signals from a controller over a high speed data link which the hub translates into electrical data, command and address signals. These signals are applied to the memory devices over busses having equivalent path lengths. The busses may also be used by the memory devices to apply data signals to the memory hub. Such data signals can be converted by the memory hub into memory signals and applied to the controller over the high speed data link. In one example, the memory hub is located in the center of the memory module.

Claims

1. A memory module comprising:

a plurality of memory devices; and

a memory hub coupled to the plurality of memory devices by a respective plurality of busses, wherein each individual one of the plurality of busses has the same physical length and couples a respective one of the plurality of memory devices to the memory hub, wherein the hub is configured to be coupled to a memory hub Of another memory module by a hub communication'"'"' link, the hub communication link configured to couple signals between the memory hubs, and wherein the hub communication link is different than the plurality of busses.

2. The memory module of claim 1, wherein the memory hub comprises an interface, the hub communication link further configured to couple the interface to an interface of another memory hub.

3. The memory module of claim 1, wherein the hub communication link comprises a point-to-point link.

4. The memory module of claim 1, wherein each individual one of the plurality of busses spans the shortest path possible between the memory hub and the plurality of memory devices.

5. The memory module of claim 1, wherein the signals comprise command, address, write data and read data signals.

6. The memory module of claim 1, wherein the memory hub is configured to be coupled to a controller by a memory link.

7. The memory module of claim 6, wherein the signals comprise signals coupled from the memory link to the memory hub.

8. The memory module of claim 7, wherein the memory hub is placed at a center of the memory module.

9. The memory module of claim 1, wherein the memory devices and the memory hub are supported by a same substrate.

10. A memory system comprising:

a controller;

a plurality of memory modules including a first memory module, and a second memory module, individual ones of the plurality of memory modules comprising;

a memory hub coupled to the controller and configured to receive data signals from the controller; and

a plurality of memory devices wherein the plurality of memory devices are physically equidistant from the memory hub and coupled to the memory hub;

a hub communications link coupled to a memory hub of the first memory module and a memory hub of the second memory module, the hub communications link configured to couple signals between the memory hubs;

a first data conduit coupled between the controller and the memory hub of the first memory module; and

a second data conduit coupled between the controller and the memory hub of the second memory module.

11. The memory system of claim 10, wherein at least one memory hub comprises:

an interface configured to couple to the hub communications link.

12. The memory system of claim 10, wherein the first data conduit and the second data conduit comprise a memory link.

13. The memory system of claim 10, wherein at least one of the first data conduit and the second data conduit comprises:

a first communication link configured to couple data signals; and

a second communication link configured to couple at least one of command and address signals.

14. The memory system of claim 10, wherein the hub communications link comprises at least one unidirectional bus.

15. A method of communicating between memory interfaces, the method comprising:

coupling a memory request to a first memory hub over a bus;

converting the memory request to at least one of command, address or data signals;

applying the at least one of command, address or data signals to at least one of a plurality of memory devices, wherein the plurality of memory devices are physically equidistant from the first memory hub; and

coupling the at least one of command, address or data signals to a second memory hub over a hub communications link.

16. The method of claim 15, wherein the at least one of command, address or data signals data comprises at least one of read or write data.

17. The method of claim 15, said applying comprising:

before coupling the at least one of command, address or data signals to a second memory hub, coupling the at least one of command, address or data signals to the plurality of memory devices.

18. The method of claim 15, said applying comprising:

before coupling the at least one of command, address or data signals to a second memory hub, determining if at least one of command, address or data signals is appropriate for at least one of the plurality of memory devices; and

coupling the at least one of command, address or data signals to at least one of the plurality of memory devices responsive to the at least one of the plurality of memory devices being appropriate to receive the at least one of command, address or data signals.

19. The method of claim 15, further comprising:

coupling a response signal to a controller over the bus.