Interface device for interfacing a main processor to processing engines and classifier engines, and methods for configuring and operating interface devices
First Claim
1. An interface device for interfacing a main processor and a processing engine, the interface comprisinga settings storage to store variables of the processing engine, the variables includinga translation of instructions into an operation code set of the processing enginea conversion of operands into a format of the processing enginea pin map of the processing enginea clock rate of the processing enginea main processor interface having a first pipe to couple to a first bus, the main processor interface to receive messages via the first bus from the main processor directed at the processing engine, wherein the first pipe has a fixed width, a fixed pin map and a fixed clock ratea decoder coupled to the settings storage toseparate the messages into instructions and operandstranslate the instructions to the operation code set of the processing engine according to the translation variable stored in the settings storageconvert the operands to the format of the processing engine according to the conversion variable stored in the settings storagea processing engine interface having a second pipe to couple to a second bus, the processing engine interface to send translated operation codes and converted operands via the second bus to the processing engine, wherein the second pipe has a configurable pin map and a configurable clock rate to be used in conformance with the processing engine pin map and the processing engine clock rate.
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Accused Products
Abstract
There is disclosed an interface device for interfacing between a main processor and one or more processing engines. The interface device is configurable, so that it may be used with a wide range of processing engines without being redesigned.
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Citations
44 Claims
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1. An interface device for interfacing a main processor and a processing engine, the interface comprising
a settings storage to store variables of the processing engine, the variables including a translation of instructions into an operation code set of the processing engine a conversion of operands into a format of the processing engine a pin map of the processing engine a clock rate of the processing engine a main processor interface having a first pipe to couple to a first bus, the main processor interface to receive messages via the first bus from the main processor directed at the processing engine, wherein the first pipe has a fixed width, a fixed pin map and a fixed clock rate a decoder coupled to the settings storage to separate the messages into instructions and operands translate the instructions to the operation code set of the processing engine according to the translation variable stored in the settings storage convert the operands to the format of the processing engine according to the conversion variable stored in the settings storage a processing engine interface having a second pipe to couple to a second bus, the processing engine interface to send translated operation codes and converted operands via the second bus to the processing engine, wherein the second pipe has a configurable pin map and a configurable clock rate to be used in conformance with the processing engine pin map and the processing engine clock rate.
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21. A method of configuring an interface device, the interface device for interfacing a main processor and a processing engine, the method comprising
providing the interface device, the interface device comprising a main processor interface and a processing engine interface the main processor interface having a first pipe coupled to a first bus for receiving messages via the first bus from the main processor directed at the processing engine, wherein the first pipe has a fixed width, a fixed pin map and a fixed clock rate the processing engine interface having a second pipe coupled to a second bus for sending translated instructions and converted operands via the second bus to the processing engine, wherein the second pipe has a configurable pin map and a configurable clock rate storing variables of the processing engine, the variables including a translation of instructions into an operation code set of the processing engine a conversion of operands into a format of the processing engine a pin map of the processing engine a clock rate of the processing engine using the second pipe in conformance with the processing engine pin map and the processing engine clock rate.
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24. A method of operating an interface device, the interface device for interfacing a main processor and a processing engine, the method comprising
storing variables of the processing engine, the variables including a translation of instructions into an operation code set of the processing engine a conversion of operands into a format of the processing engine a pin map of the processing engine a clock rate of the processing engine receiving messages via a first pipe in the interface device from the main processor directed at the processing engine, wherein the first pipe has a fixed width, a fixed pin map and a fixed clock rate decoding the messages by separating the messages into instructions and operands translating the instructions to the instruction set of the processing engine according to the translation variable stored in the settings storage converting the operands to the format of the processing engine according to the conversion variable stored in the settings storage sending the translated operation codes and the converted operands via a second pipe in the interface device to the processing engine, wherein the second pipe has a configurable pin map and a configurable clock rate and is configured in conformance with the processing engine pin map and the processing engine clock rate.
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28. An interface device for interfacing a main processor and a plurality of processing engines, the interface device comprising
a settings storage to store variables of the processing engines, respectively, the variables including a translation of instructions into an operation code set of the processing engine a conversion of operands from into a format of the processing engine a pin map of the processing engine a clock rate of the processing engine a main processor interface having a first pipe to couple to a first bus, the main processor interface to receive messages via the first pipe from the main processor directed at the processing engines, wherein the first pipe has a fixed width, a fixed pin map and a fixed clock rate, the main processor interface further to identify which of the processing engines should receive the messages a decoder coupled to the settings storage to separate messages from the main processor into instructions and operands translate the instructions from the instruction set of the main processor to the instruction set of the identified processing engine according to the translation variable stored in the settings storage for the identified processing engine convert the operand from the format of the main processor to the format of the identified processing engine according to the conversion variable stored in the settings storage for the identified processing engine a processing engine interface having plural second pipes to respectively coupled to plural second buses, the processing engine interface to send translated operation codes and converted operands via the second buses to the identified processing engines, wherein the second pipes have configurable pin maps and configurable clock rates configurable to be used in conformance with the processing engine pin map and the processing engine clock rate for the respective processing engines.
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39. A method of operating an interface device, the interface device for interfacing a main processor and a plurality of processing engines, the method comprising
storing variables of the processing engines, the variables respectively including a translation of instructions into an operation code set of the processing engine a conversion of operands into a format of the processing engine a pin map of the processing engine a clock rate of the processing engine receiving messages via a first pipe in the interface device from the main processor, wherein the first pipe has a fixed width, pin map and clock rate identifying which of the processing engines should receive the messages decoding the messages by separating the messages into instructions and operands translating the instructions to the operation code set of the identified processing engine according to the translation variable stored in the settings storage for the identified processing engine converting the operands to the format of the identified processing engine according to the conversion variable stored in the settings storage for the identified processing engine sending the translated operation codes and the converted operands via plural second pipes in the interface device to the identified processing engines, wherein the second pipes have configurable pin maps and configurable clock rates and are configured in conformance with the processing engine pin map and the processing engine clock rate of the respective processing engines.
Specification