APIC implementation for a highly-threaded x86 processor

• US 8,190,864 B1
• Filed: 10/25/2007
• Issued: 05/29/2012
• Est. Priority Date: 10/25/2007
• Status: Active Grant

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Oracle America, Inc. (Oracle Corporation)
• Inventors: Jordan, Paul J., Grohoski, Gregory F.
• Primary Examiner(s): Alrobaye, Idriss N
• Application Number:
  US11/924,491
• Time in Patent Office: 1,678 Days
• Field of Search: 712/244
• US Class Current: 712/244
• CPC Class Codes: G06F 9/4818 Priority circuits therefor

Abstract

Advanced programmable interrupt control for a multithreaded multicore processor that supports software compatible with x86 processors. Embodiments provide interrupt control for increased threads with minimal additional hardware by including in each processor core, a core advanced interrupt controller (core APIC) configured to determine a lowest priority thread of its corresponding processor core. Each core APIC reports its lowest priority thread level as a core priority to an input/output APIC. The I/O APIC routes interrupt requests to the core APIC with the lowest core priority. The selected core APIC then routes the interrupt request to the corresponding lowest priority thread. Each core APIC detects changes in priority levels of its corresponding processor core threads, and notifies the I/O APIC of any change to the corresponding core priority. Each core APIC may notify the I/O APIC as the core priority changes, or when the I/O APIC requests status from each core APIC.

Claims

1. A multithreaded multicore processor comprising:

an input/output advanced programmable interrupt controller (I/O APIC); and

a plurality of processor cores, each including;

one of a plurality of multithreaded processors configured to execute a plurality of threads; and

one of a plurality of core APICs, wherein each core APIC includes a plurality of interrupt command registers (IRCs), each of the plurality of IRCs corresponding to one of the threads of the plurality of threads of the multithreaded processor, a plurality of logical destination registers (LDRs), each of the plurality of LDRs corresponding one of the threads of the plurality of threads of the multithreaded processor, the one of a plurality of core APICs coupled to the one of the plurality of multithreaded processors and to the I/O APIC, and configured to receive an interrupt request and to route the interrupt request to a lowest priority thread of the one of the plurality of multithreaded processors.

2. The multithreaded multicore processor of claim 1, wherein each of the plurality of core APICs is configured to determine a core priority based on a thread priority level of each of the threads of the one of the plurality of multithreaded processors.

3. The multithreaded multicore processor of claim 1, wherein the I/O APIC includes a lowest priority core APIC register and an I/O APIC priority register, and is configured to:

receive a core priority from each of the plurality of core APICs;

determine a lowest priority core APIC of the plurality of core APICS, wherein the lowest priority core APIC has a lowest core priority corresponding to the lowest priority thread; and

route the interrupt request to the lowest priority core APIC.

4. The multithreaded multicore processor of claim 1, wherein each core APIC includes:

a lowest priority thread register;

a core APIC priority register; and

a core APIC coupled to each of the plurality of ICRs, to each of the plurality of LDRs, to the lowest priority thread register, and to the core APIC priority register, wherein the core APIC controller routes the interrupt request to the lowest priority thread of the multithreaded processor based on the plurality of IRCs and the plurality of LDRs.

5. The multithreaded multicore processor of claim 4, wherein the plurality of ICRs and the plurality of LDRs support a quantity of the plurality of threads greater than one of the following:

255 threads for a physical destination mode; and

60 threads for logical destination mode that uses a hierarchical cluster destination model.

6. The multithreaded multicore processor of claim 1, wherein each of the plurality of core APICs is configured to:

identify a current lowest priority thread of the plurality of threads;

detect a reduced priority level of the current lowest priority thread;

update a current lowest priority thread register to the reduced priority level; and

set a core priority to the reduced priority level.

7. The multithreaded multicore processor of claim 1, wherein each of the plurality of care APICs is configured to:

identify a current lowest priority thread of the plurality of threads;

detect an increased priority level of the current lowest priority thread;

set a core priority to a maximum level;

determine a new lowest priority thread of the plurality of threads, wherein the new lowest priority thread has a new lowest priority level of the plurality of threads;

set the new lowest priority thread as the current lowest priority thread with the new lowest priority level; and

set a core priority to the new lowest priority level.

8. The multithreaded multicore processor of claim 1, wherein each of the plurality of core APICs is configured to:

identify a current lowest priority thread of the plurality of threads;

detect a reduced priority level of one of the plurality of threads other than the current lowest priority thread, wherein the reduced priority level is lower than a priority level of the current lowest priority thread;

set the one of the plurality of threads with the reduced priority level to be the current lowest priority thread; and

set a core priority to the reduced priority level.

9. The multithreaded multicore processor of claim 1, wherein each of the plurality of core APICs is configured to notify the I/O APIC of a change in a core priority at the time of the change in the core priority, wherein the core priority is a priority level of a lowest priority thread of a corresponding one of the plurality of multithreaded processors.

10. The multithreaded multicore processor of claim 1, wherein each of the plurality of core APICs is configured to notify the I/O APIC of a change in a core priority upon a request from the I/O APIC, wherein the core priority is a priority level of a lowest priority thread of a corresponding one of the plurality of multithreaded processors.

11. A core advanced programmable interrupt controller (core APIC) comprising:

a plurality of registers, each register identifying one of a plurality of threads of one of a plurality of multithreaded processors and each register storing a priority level of the one of the plurality of threads;

a processor interface configured to communicate with the one of the plurality of multithreaded processors;

a bus interface configured to communicate with a communication bus for communication with an input/output APIC (I/O APIC) that communicates with a plurality of other core APICs; and

a core APIC wherein the core APIC includes a plurality of interrupt command registers (IRCs), each of the plurality of IRCs dedicated to one of the threads of the plurality of threads of one of the multithreaded processors, a plurality of logical destination registers (LDRs), each of the plurality of LDRs dedicated to one of the threads of the plurality of threads associated with one of the threads of one of the multithreaded processors, the core APIC coupled to the processor interface, to the bus interface, and to each of the plurality of registers, wherein the core APIC controller is configured to;

determine a current lowest priority thread of the plurality of threads;

receive an interrupt request via the bus interface; and

route the interrupt request to the current lowest priority thread.

12. The core APIC of claim 11, wherein the core APIC is further configured to determine a core priority as a priority level of the current lowest priority thread.

13. The core APIC of claim 11, wherein the core APIC is further configured to:

detect a reduced priority level of the current lowest priority thread;

update a current lowest priority thread register to the reduced priority level; and

set a core priority to the reduced priority level.

14. The core APIC of claim 11, wherein the core APIC is further configured to:

detect one of the following;

a reduced priority level of one of the plurality of threads other than the current lowest priority thread, wherein the reduced priority level is lower than a priority level of the current lowest priority thread, and

activation of the one of the plurality of threads;

set the one of the plurality of threads with the reduced priority level to be the current lowest priority thread; and

set a core priority to the reduced priority level.

15. The core APIC of claim 11, wherein the core APIC is further configured to notify the I/O APIC of a change in a lowest priority value of the current lowest priority thread, wherein the core APIC notifies the I/O APIC at the time of the change in the lowest priority value.

16. The core APIC of claim 11, wherein the core APIC is further configured to notify the I/O APIC of a change in a lowest priority value of the current lowest priority thread, wherein the core APIC notifies the I/O APIC upon a request from the I/O APIC.

17. A computing system comprising:

a peripheral device;

a memory;

an input/output advanced programmable interrupt controller (I/O APIC); and

a multithreaded multicore processor coupled to the peripheral device, to the memory, and to the I/O APIC, the multithreaded multicore processor including a plurality of processor cores, each comprising;

one of a plurality of multithreaded processors configured to execute a plurality of threads; and

one of a plurality of core APICs wherein each core APIC includes a plurality of interrupt command registers (IRCs), each of the plurality of IRCs corresponding to one of the threads of the plurality of threads of the multithreaded processor and a plurality of logical destination registers (LDRs), each of the plurality of LDRs corresponding to one of the threads of the plurality of threads of the multithreaded processor, the one of a plurality of core APICs coupled to the one of the plurality of multithreaded processors and to the I/O APIC, and configured to receive an interrupt request and to route the interrupt request to a lowest priority thread of the one of the plurality of multithreaded processors.

18. The computing system of claim 17, wherein the I/O APIC is configured to:

receive a core priority from each of the plurality of core APICs; and

route the interrupt request to a lowest priority core APIC of the plurality of core APICS, wherein the lowest priority core APIC has a lowest core priority corresponding to the lowest priority thread.

19. The computing system of claim 17, wherein each of the plurality of core APICs is configured to notify the I/O APIC of a change in a core priority, wherein the core priority is a priority level of a lowest priority thread of a corresponding one of the plurality of multithreaded processors, and wherein a quantity of the plurality of threads is greater than one of the following:

255 threads when the computing system operates in a physical destination mode; and

60 threads when the computing system operates in logical destination mode that uses a hierarchical cluster destination model.

20. The computing system of claim 17, further comprising:

a second I/O APIC coupled to the multithreaded multicore processor, and configured to manage the priority levels, of a portion of the plurality of processor cores; and

a hierarchically higher level I/O APIC coupled to the I/O APIC and to the second I/O APIC, and configured to determine a lowest priority I/O APIC.

21. A core advanced programmable interrupt controller (core APIC) comprising:

a plurality of registers, each register identifying one of a plurality of threads of one of a plurality of multithreaded processors and each register storing a priority level of the one of the plurality of threads;

a processor interface configured to communicate with the one of the plurality of multithreaded processors;

a bus interface configured to communicate with a communication bus for communication with an input/output APIC (I/O APIC) that communicates with a plurality of other core APICs; and

a core APIC wherein the core APIC includes a plurality of interrupt command registers (IRCs), each associated with one of the threads of one of the multithreaded processors, a plurality of logical destination registers (LDRs), each associated with one of the threads associated with one of the threads of one of the multithreaded processors, the core APIC coupled to the processor interface, to the bus interface, and to each of the plurality of registers, wherein the core APIC is configured to;

determine a current lowest priority thread of the plurality of threads;

receive an interrupt request via the bus interface;

route the interrupt request to the current lowest priority thread; and

detect one of the following;

an increased priority level of the current lowest priority thread;

and a deactivation of the currently lowest priority thread;

set a core priority to a maximum level;

determine a new lowest priority thread of the plurality of threads, wherein the new lowest priority thread has a new lowest priority level of the plurality of threads;

set the new lowest priority thread as the current lowest priority thread with the new lowest priority level; and

set a core priority to the new lowest priority level.