APIC implementation for a highly-threaded x86 processor
First Claim
1. A multithreaded multicore processor comprising:
- an input/output advanced programmable interrupt controller (I/O APIC); and
a plurality of processor cores, each including;
one of a plurality of multithreaded processors configured to execute a plurality of threads; and
one of a plurality of core APICs, wherein each core APIC includes a plurality of interrupt command registers (IRCs), each of the plurality of IRCs corresponding to one of the threads of the plurality of threads of the multithreaded processor, a plurality of logical destination registers (LDRs), each of the plurality of LDRs corresponding one of the threads of the plurality of threads of the multithreaded processor, the one of a plurality of core APICs coupled to the one of the plurality of multithreaded processors and to the I/O APIC, and configured to receive an interrupt request and to route the interrupt request to a lowest priority thread of the one of the plurality of multithreaded processors.
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Accused Products
Abstract
Advanced programmable interrupt control for a multithreaded multicore processor that supports software compatible with x86 processors. Embodiments provide interrupt control for increased threads with minimal additional hardware by including in each processor core, a core advanced interrupt controller (core APIC) configured to determine a lowest priority thread of its corresponding processor core. Each core APIC reports its lowest priority thread level as a core priority to an input/output APIC. The I/O APIC routes interrupt requests to the core APIC with the lowest core priority. The selected core APIC then routes the interrupt request to the corresponding lowest priority thread. Each core APIC detects changes in priority levels of its corresponding processor core threads, and notifies the I/O APIC of any change to the corresponding core priority. Each core APIC may notify the I/O APIC as the core priority changes, or when the I/O APIC requests status from each core APIC.
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Citations
21 Claims
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1. A multithreaded multicore processor comprising:
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an input/output advanced programmable interrupt controller (I/O APIC); and a plurality of processor cores, each including; one of a plurality of multithreaded processors configured to execute a plurality of threads; and one of a plurality of core APICs, wherein each core APIC includes a plurality of interrupt command registers (IRCs), each of the plurality of IRCs corresponding to one of the threads of the plurality of threads of the multithreaded processor, a plurality of logical destination registers (LDRs), each of the plurality of LDRs corresponding one of the threads of the plurality of threads of the multithreaded processor, the one of a plurality of core APICs coupled to the one of the plurality of multithreaded processors and to the I/O APIC, and configured to receive an interrupt request and to route the interrupt request to a lowest priority thread of the one of the plurality of multithreaded processors. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A core advanced programmable interrupt controller (core APIC) comprising:
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a plurality of registers, each register identifying one of a plurality of threads of one of a plurality of multithreaded processors and each register storing a priority level of the one of the plurality of threads; a processor interface configured to communicate with the one of the plurality of multithreaded processors; a bus interface configured to communicate with a communication bus for communication with an input/output APIC (I/O APIC) that communicates with a plurality of other core APICs; and a core APIC wherein the core APIC includes a plurality of interrupt command registers (IRCs), each of the plurality of IRCs dedicated to one of the threads of the plurality of threads of one of the multithreaded processors, a plurality of logical destination registers (LDRs), each of the plurality of LDRs dedicated to one of the threads of the plurality of threads associated with one of the threads of one of the multithreaded processors, the core APIC coupled to the processor interface, to the bus interface, and to each of the plurality of registers, wherein the core APIC controller is configured to; determine a current lowest priority thread of the plurality of threads; receive an interrupt request via the bus interface; and route the interrupt request to the current lowest priority thread. - View Dependent Claims (12, 13, 14, 15, 16)
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17. A computing system comprising:
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a peripheral device; a memory; an input/output advanced programmable interrupt controller (I/O APIC); and a multithreaded multicore processor coupled to the peripheral device, to the memory, and to the I/O APIC, the multithreaded multicore processor including a plurality of processor cores, each comprising; one of a plurality of multithreaded processors configured to execute a plurality of threads; and
one of a plurality of core APICs wherein each core APIC includes a plurality of interrupt command registers (IRCs), each of the plurality of IRCs corresponding to one of the threads of the plurality of threads of the multithreaded processor and a plurality of logical destination registers (LDRs), each of the plurality of LDRs corresponding to one of the threads of the plurality of threads of the multithreaded processor, the one of a plurality of core APICs coupled to the one of the plurality of multithreaded processors and to the I/O APIC, and configured to receive an interrupt request and to route the interrupt request to a lowest priority thread of the one of the plurality of multithreaded processors. - View Dependent Claims (18, 19, 20)
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21. A core advanced programmable interrupt controller (core APIC) comprising:
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a plurality of registers, each register identifying one of a plurality of threads of one of a plurality of multithreaded processors and each register storing a priority level of the one of the plurality of threads; a processor interface configured to communicate with the one of the plurality of multithreaded processors; a bus interface configured to communicate with a communication bus for communication with an input/output APIC (I/O APIC) that communicates with a plurality of other core APICs; and a core APIC wherein the core APIC includes a plurality of interrupt command registers (IRCs), each associated with one of the threads of one of the multithreaded processors, a plurality of logical destination registers (LDRs), each associated with one of the threads associated with one of the threads of one of the multithreaded processors, the core APIC coupled to the processor interface, to the bus interface, and to each of the plurality of registers, wherein the core APIC is configured to; determine a current lowest priority thread of the plurality of threads; receive an interrupt request via the bus interface; route the interrupt request to the current lowest priority thread; and detect one of the following; an increased priority level of the current lowest priority thread; and a deactivation of the currently lowest priority thread; set a core priority to a maximum level; determine a new lowest priority thread of the plurality of threads, wherein the new lowest priority thread has a new lowest priority level of the plurality of threads; set the new lowest priority thread as the current lowest priority thread with the new lowest priority level; and set a core priority to the new lowest priority level.
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Specification