Methods and software for printing materials onto a substrate

• US 8,191,018 B1
• Filed: 07/17/2008
• Issued: 05/29/2012
• Est. Priority Date: 07/17/2007
• Status: Expired due to Fees

• Current Assignee: Ensurge Micropower ASA
• Original Assignee: Kovio Incorporated (Ensurge Micropower ASA)
• Inventors: Molesa, Steven, Scher, Erik, Smith, Patrick, Kocsis, Michael
• Primary Examiner(s): Kik, Phallaka
• Application Number:
  US12/175,423
• Time in Patent Office: 1,412 Days
• Field of Search: 716/21, 716/5, 716/52, 716/53, 716/54, 716/55, 700/98, 700/120, 700/121, 382/141, 382/144, 382/145, 382/154
• US Class Current: 716/55
• CPC Class Codes: G06F 30/00 Computer-aided design [CAD]
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: H05K 3/0005 for designing circuits by computer
• CPC Class Codes: H05K 3/12 using thick film techniques, e.g. printing techniques to apply the conductive material or similar techniques for applying conductive paste or ink patterns

Abstract

Methods and software for correcting printable circuit layouts. The methods generally including steps of identifying shapes in an input circuit layout, applying a plurality of correction rules to the shapes, and producing an output printed circuit layout in accordance with the identified shapes and the correction rules. The input circuit layout generally comprises a bitmapped image or other description of at least one printable layer of at least one electronic component, device, or die. Embodiments of the present invention further allow for more precise control of spreading and effective coverage of features (e.g., source/drain terminal regions, gates, capacitors, diodes, interconnects, etc.) on a substrate by a printed ink composition including electronic materials.

Claims

1. A method for correcting printable circuit layouts, said method comprising:

identifying shapes in an input circuit layout for at least one layer on a substrate, wherein said layer comprises a material in at least one electronic component, device, or die, and said material is to be formed on said substrate by printing an ink composition;

applying a plurality of correction rules to said shapes, wherein said plurality of correction rules are derived from characteristics of said ink composition; and

producing, using a computer, an output printed circuit layout in accordance with said identified shapes and said correction rules.

2. The method of claim 1, wherein said input circuit layout comprises at least one bitmapped image file.

3. The method of claim 2, wherein said bitmapped image file comprises a losslessly compressed tagged image file format (TIFF) file.

4. The method of claim 1, wherein said input circuit layout comprises at least one circuit layout description file.

5. The method of claim 4, wherein said circuit layout description file comprises a graphic data system (GDS) circuit description database, a drawing interchange format (DXF) file, a Caltech Intermediate Form (CIF) file, a Gerber file, or a TDB database.

6. The method of claim 1, further comprising encoding said output printed circuit layout to produce at least one bitmapped image file.

7. The method of claim 6, wherein said bitmapped image file has a dot pitch or pixel size corresponding to the resolution of a specific printing process, such that each pixel represents a single droplet.

8. The method of claim 1, wherein identifying shapes in said input circuit layout comprises:

performing blob analysis to identify regions of connected pixels; and

eroding edges of said regions of connected pixels to identify rectangular regions of connected pixels.

9. The method of claim 1, wherein:

said correction rules comprise at least one rule correlating an output pixel density with one or more linear dimensions of one of said identified shapes; and

applying said correction rules comprises producing an output region in said output circuit layout, wherein said output region corresponds to said one of said identified shapes and said output region has said output pixel density.

10. The method of claim 1, wherein:

said correction rules comprise at least one rule correlating an output pixel density gradient with one or more linear dimensions of one of said identified shapes and a desired thickness for said one of said identified shapes; and

applying said correction rules comprises producing an output region in said output circuit layout, wherein said output region corresponds to said one of said identified shapes and having said output pixel density gradient.

11. The method of claim 1, wherein said correction rules correspond to ink drop characteristics for said material.

12. The method of claim 11, wherein said ink drop characteristics comprise a line drop density and/or an area drop density.

13. The method of claim 11, wherein said ink drop characteristics comprise spreading characteristics.

14. The method of claim 1, wherein said correction rules comprise at least one rule to remove a number of pixels at one or more edges of a given shape.

15. The method of claim 1, further comprising applying stitching corrections to said output printed circuit layout.

16. The method of claim 15, wherein applying said stitching corrections comprises:

determining a stitching region in said output printed circuit layout, wherein said stitching region corresponds to a location where sequential passes of an output device are predicted to overlap; and

adjusting a pixel density in said stitching region.

17. The method of claim 16, wherein adjusting said pixel density in said stitching region comprises increasing said pixel density in said stitching region.

18. The method of claim 1, further comprising applying manual corrections to said shapes after applying said correction rules.

19. The method of claim 1, further comprising identifying one or more die types and/or locations in said input circuit layout, wherein said correction rules comprise at least one correction rule corresponding to a given die type and/or location.

20. The method of claim 1, wherein said substrate is non-porous, and said layer is to be printed on said non-porous substrate from an ink.

21. The method of claim 1, wherein said correction rules comprise one or more shape correction rules and one or more wicking correction rules.

22. The method of claim 21, wherein printing comprises screen printing or intaglio printing.

23. The method of claim 1, wherein said correction rules comprise one or more drop density correction rules.

24. The method of claim 23, wherein said drop density correction rule(s) comprise reducing a droplet density or varying a droplet density.

25. The method of claim 24, wherein said drop density correction rule(s) comprise reducing said droplet density, and reducing said droplet density comprises masking pixels.

26. The method of claim 23, wherein printing comprises inkjet printing or gravure printing.

27. A non-transitory computer-readable medium comprising computer-executable instructions adapted to:

identify shapes in an input circuit layout for at least one layer on a substrate, wherein said layer comprises a material in at least one electronic component, device, or die, and said material is to be formed on said substrate by printing an ink composition;

apply a plurality of correction rules to said shapes, wherein said plurality of correction rules are derived from characteristics of said ink composition; and

produce an output printed circuit layout in accordance with said identified shapes and said correction rules.

28. The medium of claim 27, wherein said input circuit layout comprises at least one bitmapped image.

29. The medium of claim 27, wherein said computer-executable instructions are further adapted to obtain said input circuit layout from at least one GDS circuit layout description file.

30. The medium of claim 27, wherein said computer-executable instructions are further adapted to encode said output printed circuit layout to produce at least one bitmapped image file.

31. The medium of claim 27, wherein said computer-executable instructions adapted to identify shapes in said input circuit layout comprise instructions adapted to:

perform blob analysis to identify regions of connected pixels; and

erode edges of said regions of connected pixels to identify rectangular regions of connected pixels.

32. The medium of claim 27, wherein:

said correction rules comprise at least one rule correlating an output pixel density with one or more linear dimensions of one of said identified shapes; and

said computer-executable instructions adapted to apply said correction rules comprise one or more instructions adapted to produce an output region in said output circuit layout, wherein said output region corresponds to said one of said identified shapes and said output region has said output pixel density.

33. The medium of claim 27, wherein:

said correction rules comprise at least one rule correlating an output pixel density gradient with one or more linear dimensions of one of said identified shapes and a desired thickness for said one of said identified shapes; and

said computer-executable instructions adapted to apply said correction rules comprise one or more instructions adapted to produce an output region in said output circuit layout, wherein said output regions corresponds to said one of said identified shapes and having said output pixel density gradient.

34. The medium of claim 27, wherein said correction rules correspond to ink drop characteristics for said substrate.

35. The medium of claim 34, wherein said ink drop characteristics comprise a line drop density and/or an area drop density.

36. The medium of claim 34, wherein said ink drop characteristics comprise spreading characteristics.

37. The medium of claim 27, wherein said correction rules comprise at least one rule to remove a number of pixels at one or more edges of a given shape.

38. The medium of claim 27, wherein said computer-executable instructions are further adapted to perform a step of applying stitching corrections to said corrected printed circuit layout.

39. The medium of claim 38, wherein applying said stitching corrections comprises:

determining a stitching region in said output printed circuit layout, wherein said stitching region corresponds to a location where sequential passes of an output device are predicted to overlap; and

altering a pixel density in said stitching region.

40. The medium of claim 39, wherein altering said pixel density in said stitching region comprises increasing said pixel density in said stitching region.

41. The medium of claim 27, wherein said computer-executable instructions are further adapted to provide a user interface for applying manual corrections to said shapes after applying said correction rules.

42. The medium of claim 27, wherein said computer-executable instructions are further adapted to identify one or more die types and/or locations in said input circuit layout, wherein said correction rules comprise at least one correction rule corresponding to a given die type and/or location.

43. The medium of claim 27, further comprising computer-executable instructions and/or data adapted to implement said correction rules.

44. The medium of claim 27, further comprising computer-executable instructions adapted to load further computer-executable instructions and/or data into memory, wherein said further computer-executable instructions and/or data are adapted to implement said correction rules.

45. The medium of claim 27, wherein said correction rules comprise one or more shape correction rules and one or more wicking correction rules.

46. The medium of claim 45, wherein said printing comprises screen printing or intaglio printing.

47. The medium of claim 27, wherein said correction rules comprise one or more drop density correction rules.

48. The medium of claim 47, wherein said drop density correction rule(s) comprise reducing a droplet density or varying a droplet density.

49. The medium of claim 48, wherein said drop density correction rule(s) comprise reducing said droplet density, and reducing said droplet density comprises masking pixels.

50. The medium of claim 47, wherein said printing comprises inkjet printing or gravure printing.

51. A computer system comprising the medium of claim 27, a microprocessor or an application-specific integrated circuit configured to execute said instructions, and a printing device.