High-power semiconductor die packages with integrated heat-sink capability and methods of manufacturing the same

• US 8,193,043 B2
• Filed: 09/15/2010
• Issued: 06/05/2012
• Est. Priority Date: 01/02/2008
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Jeon, Oseob, Wu, Chung-Lin, Tjhia, Eddy, Dosdos, Bigildis C.
• Primary Examiner(s): Chu, Chris
• Application Number:
  US12/883,044
• Publication Number:
  US 20110059580A1
• Time in Patent Office: 629 Days
• Field of Search: 257/E21.499, 257/E23.086, 257/669, 257/694, 257/701, 257/778, 257704-707, 257/712, 257718-720, 438/106, 438/107, 438/122, 438/127, 438/117, 438/125, 363/147
• US Class Current: 438/125
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/371 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/37147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/3754 Coating
• CPC Class Codes: H01L 2224/40095 Kinked
• CPC Class Codes: H01L 2224/40225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/40245 the item being metallic
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/732 Location after the connecting process
• CPC Class Codes: H01L 2224/73221 Strap and wire connectors
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/73255 Bump and strap connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/84815 Reflow soldering
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/3675 characterised by the shape of the housing
• CPC Class Codes: H01L 23/40 Mountings or securing means for detachable cooling or heating arrangements heating H01L23/345; fixed by friction, plugs or springs
• CPC Class Codes: H01L 23/49562 : for devices being provided for in H01L29/00
• CPC Class Codes: H01L 23/49805 : the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/37 : of an individual strap connector
• CPC Class Codes: H01L 24/40 : of an individual strap connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/84 : using a strap connector
• CPC Class Codes: H01L 25/072 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/16 : the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

An exemplary semiconductor die package of the invention has a metal-oxide substrate disposed between a first surface of a semiconductor die and a heat-sinking component, with a conductive die clip or one or more electrical interconnect traces disposed between the metal-oxide substrate and the first surface of the semiconductor die. The heat-sinking component may comprise a heat sink, or an adaptor plate to which a heat sink may be coupled. The conductive die clip or electrical trace(s) provides electrical connection(s) to the first surface of the semiconductor die, while the metal-oxide substrate electrically insulates the die from the heat-sinking component, and provides a path of high thermal conductivity between the die and the heat-sinking component. The second surface of the semiconductor die may be left free to connect to a circuit board, or a leadframe or interconnect substrate may be attached to it.

Claims

1. A method of manufacturing a semiconductor die package, the method comprising:

assembling at least one semiconductor die, at least one electrical trace, and a metal-oxide substrate together, the at least one semiconductor die having a first surface, a second surface, a first electrically conductive region disposed on the die'"'"'s first surface, and second electrically conductive region disposed on the die'"'"'s second surface, the components being assembled such that the at least one electrical trace is disposed between the first surface of the at least one semiconductor die and a first surface of the metal-oxide substrate, such that the first electrically conductive region of the die is electrically coupled to a first portion of the at least one electrical trace, and such that the die does not occlude a second portion of the at least one electrical trace;

assembling the metal-oxide substrate and a heat-sinking component together such that a second surface of the metal-oxide substrate and a mounting surface of the heat-sinking component face one another; and

maintaining the second electrically conductive region disposed on the second surface of the at least one semiconductor die uncovered such that the semiconductor die package is mountable to a substrate with said second electrically conductive region abutting the substrate.

2. The method of claim 1 wherein assembling the at least one semiconductor die, at least one electrical trace, and a metal-oxide substrate together comprises:

forming the at least one electrical trace over the first surface of the metal-oxide substrate; and

assembling the metal-oxide substrate and at least one electrical trace with the at least one semiconductor die.

3. The method of claim 1 wherein assembling the at least one semiconductor die, at least one electrical trace, and a metal-oxide substrate together comprises:

forming an adhesion layer over the first surface of a metal-oxide substrate;

forming the at least one electrical trace over the adhesion layer; and

assembling the metal-oxide substrate and at least one electrical trace with the at least one semiconductor die.

4. The method of claim 1 wherein the at least one electrical trace is provided by a leadframe.

5. The method of claim 1 further comprising forming a body of electrically insulating material around the metal-oxide substrate and at least a portion of the at least one semiconductor die.

6. The method of claim 1 wherein the heat-sinking component comprises at least one of:

a heat sink with area of the second surface being greater than the area of the mounting surface, and a heat-sink adapter plate with an adaptor surface as the component'"'"'s second surface.

7. The method of claim 1 wherein the heat-sinking component comprises a base with a first surface and a second surface opposite to the base'"'"'s first surface, and a plurality fins disposed at the base'"'"'s second surface and integrally formed with the base, and wherein the base'"'"'s first surface faces the metal-oxide substrate, and wherein the method further comprises forming a body of electrically insulating material around the metal-oxide substrate, at least a portion of the at least one semiconductor die, and at least a portion of the base.

8. A method of manufacturing a semiconductor die package, the method comprising:

assembling a leadframe, a die clip, and at least one semiconductor die together as a first sub-assembly, the at least one semiconductor die having a first surface, a second surface, a first electrically conductive region disposed on the die'"'"'s first surface, and second electrically conductive region disposed on the die'"'"'s second surface, the leadframe having a first conductive region and a second conductive region electrically isolated from the first conductive region, the die clip having a major portion, a minor portion, and a bridge portion between the major and minor portions, the major portion having a first surface and a second surface opposite to its first surface, the minor portion having a first surface and a second surface opposite to its first surface, the semiconductor die being assembled such that the die'"'"'s first electrically conductive region is electrically coupled to the leadframe'"'"'s first electrically conductive region, and the die clip being assembled such that the first surface of its major portion is disposed over the second surface of the semiconductor die and electrically coupled thereto, and such that the first surface of the minor portion is disposed over the second conductive region of the leadframe and electrically coupled thereto; and

assembling a heat-sinking component, a metal-oxide substrate, and the first sub-assembly together as a second sub-assembly such that the metal-oxide substrate is disposed between the heat-sinking component and the first sub-assembly.

9. The method of claim 8 wherein assembling the leadframe, die clip, and at least one semiconductor die together comprises:

attaching the at least one semiconductor die and the leadframe together, and thereafter attaching the die clip to the at least one semiconductor die and the leadframe.

10. The method of claim 8 wherein assembling the leadframe, die clip, and at least one semiconductor die together comprises:

aligning the components with solder material disposed between them, and thereafter reflowing the solder material.

11. The method of claim 8 further comprising forming a body of electrically insulating material around the metal-oxide substrate and at least a portion of the at least one semiconductor die.

12. The method of claim 8 wherein the heat-sinking component comprises at least one of:

a heat sink with area of the second surface being greater than the area of the mounting surface, and a heat-sink adapter plate with an adaptor surface as the component'"'"'s second surface.

13. A method of manufacturing a semiconductor die package, the method comprising:

assembling at least one semiconductor die, at least one electrical trace, and a metal-oxide substrate together, the at least one semiconductor die having a first surface, a second surface, a first electrically conductive region disposed on the die'"'"'s first surface, and second electrically conductive region disposed on the die'"'"'s second surface, the components being assembled such that the at least one electrical trace is disposed between the first surface of the at least one semiconductor die and a first surface of the metal-oxide substrate, such that the first electrically conductive region of the die is electrically coupled to a first portion of the at least one electrical trace, and such that the die does not occlude a second portion of the at least one electrical trace;

assembling the metal-oxide substrate and a heat-sinking component together such that a second surface of the metal-oxide substrate and a mounting surface of a heat-sinking component face one another; and

disposing an electrically insulating material around the metal-oxide substrate and the at least one semiconductor die to form a housing such that the housing leave the second electrically conductive region disposed on the die'"'"'s second surface uncovered such that the semiconductor die package is mountable to a substrate with said second electrically conductive region abutting the substrate.

14. The method of claim 13 wherein assembling the at least one semiconductor die, at least one electrical trace, and a metal-oxide substrate together comprises:

forming the at least one electrical trace over the first surface of the metal-oxide substrate; and

assembling the metal-oxide substrate and at least one electrical trace with the at least one semiconductor die.

15. The method of claim 13 wherein assembling the at least one semiconductor die, at least one electrical trace, and a metal-oxide substrate together comprises:

forming an adhesion layer over the first surface of a metal-oxide substrate;

forming the at least one electrical trace over the adhesion layer; and

assembling the metal-oxide substrate and at least one electrical trace with the at least one semiconductor die.

16. The method of claim 13 wherein the at least one electrical trace is provided by a leadframe.

17. The method of claim 13 wherein the heat-sinking component comprises at least one of:

a heat sink with area of the second surface being greater than the area of the mounting surface, and a heat-sink adapter plate with an adaptor surface as the component'"'"'s second surface.

18. The method of claim 13 wherein the heat-sinking component comprises a base with a first surface and a second surface opposite to the base'"'"'s first surface, and a plurality fins disposed at the base'"'"'s second surface and integrally formed with the base, and wherein the base'"'"'s first surface faces the metal-oxide substrate, and

wherein disposing an electrically insulating material further comprises disposing the electrically insulating material around at least a portion of the base.