Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby

• US 8,193,567 B2
• Filed: 12/11/2008
• Issued: 06/05/2012
• Est. Priority Date: 09/28/2005
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Kavalieros, Jack T., Brask, Justin K., Doyle, Brian S., Shah, Uday, Datta, Suman, Metz, Matthew V., Chau, Robert S., Doczy, Mark L.
• Primary Examiner(s): Quach, Tuan N.
• Application Number:
  US12/333,248
• Publication Number:
  US 20090090976A1
• Time in Patent Office: 1,272 Days
• Field of Search: 257/288, 257/368, 257/369, 257/E29.264
• US Class Current: 257/288
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 29/1037 and non-planar channel resulting from the gate electrode disposition, e.g. within a trench, H01L29/42356
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate

Abstract

A process capable of integrating both planar and non-planar transistors onto a bulk semiconductor substrate, wherein the channel of all transistors is definable over a continuous range of widths.

Claims

1. A circuit device comprising:

a microprocessor cache comprising static random access memory (SRAM) formed on a bulk semiconductor substrate, the cache further including;

a first non-planar transistor, wherein the first non-planar transistor includes a first non-planar semiconductor body having a first gate-coupled sidewall height; and

a second non-planar transistor, wherein the second non-planar transistor includes a second non-planar semiconductor body with a second gate-coupled sidewall height, different than the first gate coupled sidewall height, to form two multi-gate transistors of differing channel widths within the cache, wherein the first non-planar semiconductor body further comprises a first active region having a first top surface and wherein the second non-planar semiconductor body further comprises a second active area having a second top surface substantially coplanar with the first top surface;

and the circuit device further comprising a microprocessor core comprising a logic region formed on the bulk semiconductor substrate, the logic region including a planar transistor, wherein the planar transistor further comprises;

a third active region having sidewalls substantially covered by an adjacent third isolation region on the bulk semiconductor substrate;

a third gate insulator on a top surface of the third active region;

a third gate electrode on the third gate insulator; and

a third pair of source/drain regions on opposite sides of the third gate electrode.

2. The microprocessor of claim 1, wherein a top surface of the third active region is coplanar with both the first second active regions.

3. The microprocessor of claim 1, wherein the planar transistor has a larger current carrying channel width than at least one of the first and second non-planar transistors.

4. The microprocessor of claim 1, wherein the channel regions of the first and second non-planar transistors are undoped and wherein the channel region of the planar transistor is doped.