Trench type semiconductor device and fabrication method for the same

• US 8,193,579 B2
• Filed: 07/29/2009
• Issued: 06/05/2012
• Est. Priority Date: 07/29/2008
• Status: Active Grant

• Current Assignee: ROHM Co., Ltd.
• Original Assignee: ROHM Co., Ltd.
• Inventors: Yoshimochi, Kenichi
• Primary Examiner(s): Ngo, Ngan
• Application Number:
  US12/511,458
• Publication Number:
  US 20100025759A1
• Time in Patent Office: 1,042 Days
• Field of Search: 257/329, 257/330, 257/331, 257/332, 257/333, 257/334, 257/E29.118, 257/E29.131
• US Class Current: 257/331
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

The trench type semiconductor device includes a gate insulating film placed on the bottom surface and the sidewall surface of the trench formed from the surface of a first base layer; a gate electrode placed on the gate insulating film and fills up into a trench; an interlayer insulating film covering the gate electrode; a second base layer placed on the surface of the first base layer, and is formed more shallowly than the bottom surface of the trench; a source layer placed on the surface of the second base layer; a source electrode connected to the second base layer in the bottom surface of a self-aligned contact trench formed in the second base layer by applying the interlayer insulating film as a mask, and is connected to the source layer in the sidewall surface; a drain layer placed at the back side of the first base layer; and a drain electrode placed at the drain layer, for achieving the minute structure by the self-alignment, reducing the on resistance, and improving the breakdown capability, and providing a fabrication method for the same.

Claims

1. A trench type semiconductor device comprising:

a first base layer of a first conductivity type having high resistivity;

a gate insulating film placed on a bottom surface and a sidewall surface of a trench formed from a surface of the first base layer;

a gate electrode placed on the gate insulating film and fills up into the trench;

an interlayer insulating film placed by covering the gate electrode;

a second base layer of a second conductivity type placed on the surface of the first base layer, and is formed more shallowly than a bottom surface of the trench;

a first main electrode layer of the first conductivity type placed on a surface of the second base layer;

a first main electrode is connected to the second base layer in a bottom surface of a self-aligned contact trench, and is connected to the first main electrode layer in a sidewall surface of the self-aligned contact trench, the self-aligned contact trench being configured to pass through the first main electrode layer and being formed in the second base layer by applying the interlayer insulating film as a mask, the first main electrode being disposed all over a device structure toward the self-aligned contact trench;

a second main electrode layer placed at a back side of the first base layer; and

a second main electrode placed at the second main electrode layer;

wherein the interlayer insulating film includes arsenic implanted by ion implantation as an impurity, and an impurity concentration of arsenic in the interlayer insulating film is higher than impurity concentrations of the first base layer, the second base layer, and the first main electrode layer.

2. The trench type semiconductor device according to claim 1, wherein

the interlayer insulating film is formed with a LOCOS oxidation film, and is placed by covering a part of the gate insulating film and a part of the first main electrode layer.

3. The trench type semiconductor device according to claim 1, wherein

the bottom surface of the self-aligned contact trench is provided with a body contact layer with the second conductivity type whose impurity concentration is higher than the second base layer.

4. The trench type semiconductor device according to claim 1, wherein

the first main electrode is placed all over a device surface.

5. The trench type semiconductor device according to claim 1, wherein

the first main electrode provides with a barrier metal layer on an underlying.

6. The trench type semiconductor device according to claim 1, wherein

in the first base layer and the second base layer, a surface orientation is (100).

7. The trench type semiconductor device according to claim 1, wherein

the trench formed in the first base layer has a rectangular plane pattern.

8. The trench type semiconductor device according to claim 1, wherein

both the bottom surface and the sidewall surface of the trench formed in the first base layer have the surface orientation of (100).

9. The trench type semiconductor device according to claim 1, wherein

both the bottom surface and the sidewall surface of the self-aligned contact trench have the surface orientation of (100).

10. The trench type semiconductor device according to claim 1, wherein

the self-aligned contact trench has a lattice-like pattern.

11. The trench type semiconductor device according to claim 1, wherein

the self-aligned contact trench has a zigzagged lattice-like pattern.

12. The trench type semiconductor device according to claim 1, wherein

the self-aligned contact trench has a stripe shaped pattern.