Shielded gate trench MOSFET device and fabrication

• US 8,193,580 B2
• Filed: 08/14/2009
• Issued: 06/05/2012
• Est. Priority Date: 08/14/2009
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Inc. (Alpha & Omega Semiconductor, Ltd.)
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Chen, John, Lee, Il Kwan, Chang, Hong, Li, Wenjun, Bhalla, Anup, Yilmaz, Hamza
• Primary Examiner(s): Richards, N Drew
• Assistant Examiner(s): CARPENTER, ROBERT K
• Application Number:
  US12/583,191
• Publication Number:
  US 20110037120A1
• Time in Patent Office: 1,026 Days
• Field of Search: 257/331
• US Class Current: 257/331
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device embodiment includes a substrate, an active gate trench in the substrate, and an asymmetric trench in the substrate. The asymmetric trench has a first trench wall and a second trench wall, the first trench wall is lined with oxide having a first thickness, and the second trench wall is lined with oxide having a second thickness that is different from the first thickness. Another semiconductor device embodiment includes a substrate, an active gate trench in the substrate; and a source polysilicon pickup trench in the substrate. The source polysilicon pickup trench includes a polysilicon electrode, and top surface of the polysilicon electrode is below a bottom of a body region. Another semiconductor device includes a substrate, an active gate trench in the substrate, the active gate trench has a first top gate electrode and a first bottom source electrode, and a gate runner trench comprising a second top gate electrode and a second bottom source electrode. The second top gate electrode is narrower than the second bottom source electrode.

Claims

1. A semiconductor device, comprising:

a substrate;

an active gate trench in the substrate;

an asymmetric trench in the substrate; and

a top electrode and a bottom electrode disposed within the asymmetric trench;

wherein;

the asymmetric trench has a first trench wall that is adjacent to a termination region and a second trench wall that is adjacent to the active gate trench;

the asymmetric trench has an asymmetric region and a symmetric region;

in the asymmetric region, an oxide layer between the first trench wall and the top electrode is substantially thicker than an oxide layer between the second trench wall and the top electrode; and

in the symmetric region, an oxide layer between the first trench wall and the bottom electrode has substantially the same thickness as an oxide layer between the second trench wall and the bottom electrode.

2. The semiconductor device of claim 1, wherein the semiconductor device is a Metal Oxide Semiconductor Field Effect Transistor (MOSFET).

3. The semiconductor device of claim 1, wherein the asymmetric trench is a termination trench that separates a high potential region from a low potential region.

4. The semiconductor device of claim 3, wherein the asymmetric trench further serves as a gate runner that connects with a gate in the active gate trench.

5. The semiconductor device of claim 1, wherein the active gate trench is lined with oxide having an active gate oxide thickness that is substantially the same as the second oxide layer.

6. The semiconductor device of claim 1, wherein the top electrode is narrower in width than the bottom electrode.

7. The semiconductor device of claim 1, wherein the active gate trench includes a top gate electrode and a bottom source electrode;

and the top gate electrode is wider in width than the bottom source electrode.

8. The semiconductor device of claim 1, wherein the termination region is adjacent to the asymmetric trench.

9. The semiconductor device of claim 1, further comprising a source polysilicon contact trench in the substrate;

wherein;

the source polysilicon contact trench includes a polysilicon electrode; and

top surface of the polysilicon electrode is below a bottom of a body region.

10. The semiconductor device of claim 1, further comprising a gate contact hole directly disposed on top of the top electrode in the asymmetric trench.

11. The semiconductor device of claim 1, wherein the asymmetric trench is wider than the active gate trench.