Trench-based power semiconductor devices with increased breakdown voltage characteristics

• US 8,193,581 B2
• Filed: 04/08/2009
• Issued: 06/05/2012
• Est. Priority Date: 12/08/2008
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Yedinak, Joseph A., Probst, Dean E., Challa, Ashok, Calafut, Daniel
• Primary Examiner(s): WRIGHT, TUCKER J
• Application Number:
  US12/420,711
• Publication Number:
  US 20100140697A1
• Time in Patent Office: 1,154 Days
• Field of Search: 257330-334, 257/341, 257/E29.257, 257/E29.201
• US Class Current: 257/334
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 29/0611 for increasing or controlling the breakdown voltage of reverse biased devices H01L29/0661 takes precedence
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/872 Schottky diodes
• CPC Class Codes: H01L 29/8725 of the trench MOS barrier type [TMBS]

Abstract

Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed.

Claims

1. A semiconductor device comprising:

a first trench extending into a semiconductor region;

a first dielectric layer lining opposing sidewalls of the first trench, the first dielectric layer being thicker along one of the opposing sidewalls than along the other;

a gate electrode disposed in the first trench;

a plurality of trenches extending into the semiconductor region, each of the plurality of trenches having opposing sidewalls lined with a dielectric layer and a gate electrode disposed between the sidewalls, the dielectric layer of each trench having the same thickness along the portions of both the opposing sidewalls that face the gate electrode;

a second trench extending into the semiconductor region;

a second dielectric layer lining opposing sidewalls of the second trench, the second dielectric layer being thicker along one of the opposing sidewalls of the second trench than along the other; and

a gate electrode disposed in the second trench; and

wherein the first and second trenches and the plurality of trenches are all stripe-shaped, and the plurality of trenches are disposed between the first and second trenches.

2. The semiconductor device of claim 1 wherein the first trench and the plurality of trenches have the same width.

3. The semiconductor device of claim 1 wherein the gate electrode in the first trench has a smaller width than the gate electrode in each of the plurality of trenches.

4. The semiconductor device of claim 1 further comprising:

well regions of a first conductivity type extending in the semiconductor region between each pair of adjacent trenches; and

source regions of a second conductivity type disposed in the well regions adjacent to each of the opposing sidewalls of each of the plurality of trenches; and

wherein the first trench does not have a source region disposed adjacent to at least one of its opposing sidewalls.

5. A semiconductor device comprising:

a first trench extending into a semiconductor region;

a first dielectric layer lining opposing sidewalls of the first trench, the first dielectric layer being thicker along one of the opposing sidewalls than along the other;

a gate electrode disposed in the first trench;

a plurality of trenches extending into the semiconductor region, each of the plurality of trenches having opposing sidewalls lined with a dielectric layer and a gate electrode disposed between the sidewalls, the dielectric layer of each trench having the same thickness along the portions of both the opposing sidewalls that face the gate electrode, wherein the plurality of trenches are disposed to a first side of the first trench; and

a second trench disposed to a second side of the first trench, the second trench having a first side wall, a second side wall, a conductive body disposed between the side walls.

6. The semiconductor device of claim 5, further comprising a well region of a first conductivity type disposed in the semiconductor layer and between the first and second trenches.

7. A semiconductor device comprising:

a plurality of parallel trenches extending in a semiconductor region of a semiconductor die, each trench having a shield electrode and a gate electrode vertically stacked therein, the gate and shield electrodes being insulated from each other, each trench further having a first end facing a first edge of the semiconductor die, and a second end;

wherein the plurality of parallel trenches are bounded on two sides by two end trenches that extend in parallel with the plurality of trenches but do not encircle the plurality of the trenches, each end trench having a shield electrode disposed therein;

a plurality of mesas disposed between the trenches, each mesa having a width between adjacent trenches and an n-doped drift region, wherein the product of the mesa width and the doping concentration of the mesa'"'"'s drift region is in the range of 1×

10¹¹ to 1×

10¹³ dopant atoms per square centimeter; and

a first portion of the semiconductor region disposed between the first ends of the plurality of parallel trenches and the first edge of the semiconductor die; and

wherein the first portion does not have a perpendicular termination trench disposed therein.

8. The semiconductor device of claim 7, wherein the device does not have a well region of a first conductivity type disposed at the ends of the parallel trenches.

9. The semiconductor device of claim 7, wherein the semiconductor device comprises a MOSFET structure or an IGBT structure.

10. A semiconductor device disposed on a semiconductor die, the semiconductor device comprising:

a semiconductor layer disposed on the semiconductor die and having a first surface and a second surface;

a first trench disposed at the first surface of the semiconductor layer and having a first end facing a first edge of the semiconductor die, and a second end;

a second trench disposed at the first surface of the semiconductor layer and having a first end adjacent to the first end of the first trench and facing the first edge of the semiconductor die, and a second end;

a gate electrode disposed in the first and second trenches;

a first termination trench disposed parallel to the first trench and along a side of the first trench such that the first trench is disposed between the first termination trench and the second trench;

a shield electrode disposed in the first termination trench; and

a first portion of the semiconductor layer disposed between the first ends of the first and second trenches and the first edge of the semiconductor die; and

wherein the first portion does not have a perpendicular termination trench disposed at the first surface of the semiconductor layer.

11. The semiconductor device of claim 10 wherein the first portion does not have a well region of a first conductivity type disposed between the first and second trenches.

12. The semiconductor device of claim 10, further comprising a mesa disposed between the first and second trenches, the mesa having a width between the trenches and an n-doped drift region, wherein the product of the mesa width and the doping concentration of the mesa'"'"'s drift region is in the range of 1×

10¹¹ to 1×

10¹³ dopant atoms per square centimeter.

13. A trench shielded Schottky barrier rectifier semiconductor device disposed on a semiconductor die, the trench shielded Schottky barrier rectifier semiconductor device comprising:

a semiconductor layer disposed on the semiconductor die and having a first surface and a second surface;

a first trench disposed at the first surface of the semiconductor layer and having a first end facing a first edge of the semiconductor die, and a second end;

a second trench disposed at the first surface of the semiconductor layer and having a first end adjacent to the first end of the first trench and facing the first edge of the semiconductor die, and a second end;

a first termination trench disposed parallel to the first trench and along a side of the first trench such that the first trench is disposed between the first termination trench and the second trench;

a shield electrode disposed in the first and second trenches and in the first termination trench;

a first portion of the semiconductor layer disposed between the first ends of the first and second trenches and the first edge of the semiconductor die; and

a Schottky barrier metal disposed between the first and second trenches, and between the trench ends; and

wherein the first portion does not have a perpendicular termination trench disposed at the first surface of the semiconductor layer.

14. The semiconductor device of claim 13, wherein the device does not have a p-doped region disposed at an end of the Schottky barrier metal.

15. The semiconductor device of claim 13, wherein a p-doped region is disposed between the ends of the parallel trenches at an end edge of the Schottky barrier metal, said p-doped region being spaced from the ends of the parallel trenches.

16. A semiconductor device comprising:

a first trench extending into a semiconductor region;

a first dielectric layer lining opposing sidewalls of the first trench, the first dielectric layer being thicker along one of the opposing sidewalls than along the other;

a gate electrode disposed in the first trench;

a plurality of trenches extending into the semiconductor region, each of the plurality of trenches having opposing sidewalls lined with a dielectric layer and a gate electrode disposed between the sidewalls, the dielectric layer of each trench having the same thickness along the portions of both the opposing sidewalls that face the gate electrode;

a plurality of well regions of a first conductivity type extending in the semiconductor region between each pair of adjacent trenches; and

a plurality of source regions of a second conductivity type disposed in the well regions adjacent to each of the opposing sidewalls of each of the plurality of trenches; and

wherein the first trench does not have source regions disposed adjacent to either of its opposing sidewalls.