Semiconductor device

• US 8,193,608 B2
• Filed: 08/01/2011
• Issued: 06/05/2012
• Est. Priority Date: 03/01/2007
• Status: Active Grant

• Current Assignee: Pannova Semic, LLC (Vector Capital Corporation)
• Original Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Inventors: Yabu, Hiroaki, Kogami, Toshihiro, Arai, Katsuya
• Primary Examiner(s): Pert, Evan
• Assistant Examiner(s): Rodela, Eduardo A
• Application Number:
  US13/195,648
• Publication Number:
  US 20110284963A1
• Time in Patent Office: 309 Days
• Field of Search: 257/565, 257/575, 257/773, 257/774, 257/775, 257/786, 257/E29.031, 257/E29.034, 257/E29.112, 257/E29.114
• US Class Current: 257/565
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0266 using field effect transistors as protective elements
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate

Abstract

A semiconductor device includes: a gate electrode formed above a semiconductor region; a drain region and a source region formed in portions of the semiconductor region located below sides of the gate electrode in a gate length direction, respectively; a plurality of drain contacts formed on the drain region to be spaced apart in a gate width direction of the gate electrode; and a plurality of source contacts formed on the source region to be spaced apart in the gate width direction of the gate electrode. The intervals between the drain contacts are greater than the intervals between the source contacts.

Claims

1. A semiconductor device comprising:

a well region of a first conductivity type formed in a semiconductor region;

a collector region of a second conductivity type and an emitter region of the second conductivity type formed in the well region;

a plurality of collector contacts formed on the collector region to be spaced apart in a width direction of a transistor; and

a plurality of emitter contacts formed on the emitter region to be spaced apart in the transistor width direction,

wherein the intervals between the collector contacts are greater than the intervals between the emitter contacts.

2. The device of claim 1,

wherein the plurality of collector contacts are aligned in multiple lines in parallel with the transistor width direction.

3. The device of claim 1,

wherein the plurality of emitter contacts are aligned in multiple lines in parallel with the transistor width direction.

4. A semiconductor device comprising:

a first transistor for electrostatic discharge protection; and

a second transistor constituting a logic circuit,

wherein the first transistor includes;

a well region of a first conductivity type formed in a first semiconductor region;

a collector region of a second conductivity type and an emitter region of the second conductivity type formed in the well region;

a plurality of collector contacts formed on the collector region to be spaced apart in a width direction of a transistor; and

at least one emitter contact formed on the emitter region;

the second transistor includes;

a first diffusion region and a second diffusion region formed in a second semiconductor region;

a plurality of first contacts formed to be spaced apart on the first diffusion region; and

a plurality of second contacts formed to be spaced apart on the second diffusion region, and

the intervals between the collector contacts are greater than the intervals between the first contacts and between the second contacts.

5. The device of claim 4,

wherein the at least one emitter contact comprises a plurality of emitter contacts, and the plurality of emitter contacts are formed to be spaced apart in the transistor width direction, and

the intervals between the emitter contacts are greater than the intervals between the first contacts and between the second contacts.

6. The device of claim 5,

wherein the plurality of emitter contacts are aligned in multiple lines in parallel with the transistor width direction.

7. The device of claim 6,

wherein the intervals between the collector contacts are from 1.1 times to 5 times of the intervals between the first contacts and between the second contacts, and the intervals between the emitter contacts are from 1.1 times to 5 times of the intervals between the first contacts and between the second contacts.

8. The device of claim 5,

wherein the intervals between the collector contacts are from 1.1 times to 5 times of the intervals between the first contacts and between the second contacts and the intervals between the emitter contacts are from 1.1 times to 5 times of the intervals between the first contacts and between the second contacts.

9. The device of claim 4,

wherein the plurality of collector contacts are aligned in multiple lines in parallel with the transistor width direction.

10. The device of claim 9,

wherein the intervals between the collector contacts are from 1.1 times to 5 times of the intervals between the first contacts and between the second contacts, and the intervals between the emitter contacts are equal to the intervals between the first contacts and between the second contacts.

11. The device of claim 4,

wherein the intervals between the collector contacts are from 1.1 times to 5 times of the intervals between the first contacts and between the second contacts.

12. The device of claim 4,

wherein the at least one emitter contact comprises a plurality of emitter contacts, and the plurality of emitter contacts are formed to be spaced apart in the width direction of the transistor, and

the intervals between the emitter contacts are equal to the intervals between the first contacts and between the second contacts.

13. The device of claim 12,

wherein the intervals between the collector contacts are from 1.1 times to 5 times of the intervals between the first contacts and between the second contacts.