Battery apparatus, battery control apparatus, and motor drive unit

• US 8,193,763 B2
• Filed: 02/10/2011
• Issued: 06/05/2012
• Est. Priority Date: 03/06/2007
• Status: Active Grant

• Current Assignee: Hitachi Astemo Ltd. (Hitachi, Ltd.)
• Original Assignee: Hitachi Vehicle Energy, Ltd. (Hitachi, Ltd.)
• Inventors: Kawata, Takahiro, Emori, Akihiko, Kawahara, Youhei, Kudo, Akihiko
• Primary Examiner(s): TSO, EDWARD H
• Application Number:
  US13/024,739
• Publication Number:
  US 20110187326A1
• Time in Patent Office: 481 Days
• Field of Search: 320/107, 320/114, 320/116, 320/128, 320/132, 320/149
• US Class Current: 320/107
• CPC Class Codes: B60L 58/20 having different nominal voltages
• CPC Class Codes: G01R 31/396 Acquisition or processing of data for testing or for monitoring individual cells or groups of cells within a battery
• CPC Class Codes: H01M 10/425 Structural combination with electronic components, e.g. electronic circuits integrated to the outside of the casing printed circuits H05K1/00
• CPC Class Codes: H01M 2010/4271 Battery management systems including electronic circuits, e.g. control of current or voltage to keep battery in healthy state, cell balancing
• CPC Class Codes: H01M 2010/4278 Systems for data transfer from batteries, e.g. transfer of battery parameters to a controller, data transferred between battery controller and main controller
• CPC Class Codes: Y02E 60/10 Energy storage using batteries
• CPC Class Codes: Y02T 10/70 Energy storage systems for electromobility, e.g. batteries
• CPC Class Codes: Y02T 90/16 Information or communication technologies improving the operation of electric vehicles

Abstract

The present invention provides enhanced serial communication reliability in a situation where a plurality of cell controllers and a battery controller are daisy-chained to form a serial communication configuration. While the plurality of cell controllers and the battery controller are daisy-chained to form a serial communication configuration, the battery controller or each cell controller includes a communication speed detection means, which detects the communication speed of data input from an additional controller, and a reception timing correction means, which corrects the reception timing for data input from the additional controller in accordance with the communication speed detected by the communication speed detection means.

Claims

1. A battery apparatus comprising:

a battery module in which a plurality of unit battery cells are series-connected while a plurality of battery cells are series-connected electrically in each of the unit battery cells;

first control apparatuses, one of which is provided for each of the plurality of unit battery cells and is connected electrically to the plurality of battery cells of the associated unit battery cell;

a first signal transmitting path, which is constructed by connecting said first control apparatuses electrically, and which transmits a signal serially between said first control apparatuses;

a second control apparatus; and

a second signal transmitting path, which provides an insulating means for insulating an electrical connection, and which transmits a signal through said insulating means between the first control apparatuses and said second control apparatus which are connected electrically and serially;

wherein the signal which transmits through said first transmitting path and said second transmitting path provides a plurality of areas including a synchronous field and data byte, and a serial data signal including a plurality of signals having high levels and low levels;

wherein at least one of each of the first control apparatuses and said second control apparatus comprises

a speed detection section for detecting the speed of the serial data signal from the signal which is written in the synchronous field of the serial data signal which is input from an additional control apparatus,

a reception timing defining section for defining the reception timing for the serial data signal in accordance with the speed detected by the speed detection section, and

a signal reading section for reading in the serial data signal at the timing of the reception timing defining signal.

2. A battery apparatus according to claim 1,

wherein the speed detection section calculates an average time of the high level and an average time of the low level in the synchronous field of the serial data signal, calculates a period of the serial data signal from the sum of the average time of the high level and the average time of the low level, and outputs the calculated period of the serial data signal to a receiving timing defining signal output section.

3. A battery apparatus according to claim 2,

wherein the receiving timing defining signal output section outputs a receiving timing defining signal which has the same period as the period of the serial data signal output from the speed detection section, and

wherein the receiving timing defining signal is a repeating signal of high levels and low levels, and is constructed by a plurality of high levels and low levels.

4. A battery apparatus according to claim 3,

wherein the signal reading section reads in the serial data signal at a stand-up timing of a high level signal of the receiving timing defining signal.

5. A battery apparatus according to claim 1,

wherein the first control apparatuses detect voltages and abnormality of the plurality of battery cells in the corresponding unit battery cells, respectively, and

wherein the second control apparatus writes in a command for requesting the acquisition of the voltage of the plurality of battery cells, which are detected by the first control apparatuses, respectively, or a command for requesting the acquisition of the abnormal flag of the plurality of battery cells, which are detected by the first control apparatuses, respectively, into a data byte of the serial data, and outputs to the second signal transmitting path.

6. A battery apparatus according to claim 5,

wherein the second control apparatus outputs the serial data signal in which the command for requesting the acquisition of the voltage of the plurality of battery cells is written into the data byte to the first control apparatuses sequentially, and

outputs the serial data signal in which the command for requesting the acquisition of the abnormal flag of the plurality of battery cells to all of the first control apparatuses is written into the data byte, after transmitting the serial data signal in which the command for requesting the acquisition of the voltage of one of the battery cell written into the data byte, and during transmitting the serial data signal in which the command for requesting the acquisition of the voltage of the next battery cell written into the data byte,

wherein each of the first control apparatuses outputs a signal in which a data of the respective voltage relating the plurality of battery cells of the corresponding unit battery cells in accordance with the serial data signal in which the command for requesting the acquisition of the abnormal flag of the plurality of battery cells to all of the first control apparatuses is written into the data byte of the received data signal to the first signal transmitting path or the second signal transmitting path, respectively, and

each of the first control apparatuses outputs a signal in which an abnormal flag which indicates an abnormal state of the plurality of battery cells of the corresponding unit battery cells in accordance with the serial data signal in which the command for requesting the acquisition of the abnormal flag of the plurality of battery cells to all of the first control apparatuses is written into the data byte of the received data signal to the first signal transmitting path or the second signal transmitting path, and

wherein the second control apparatus inputs the serial data signal in which the data relating the voltage of the battery cell is written into the data byte and the serial data signal in which the abnormal flag indicating the abnormal state of the battery cell is written into the data byte alternatively from the second signal transmitting path.

7. A battery apparatus according to claim 1,

wherein each of the first control apparatuses is constructed by an integrated circuit.

8. A battery apparatus according to claim 1,

wherein a circular signal transmitting path is constructed by the first signal transmitting path and the second signal transmitting path.

9. A battery apparatus according to claim 1,

wherein the serial data signal provides an area of an identifier in which an information of an ID number for specifying one of the first control apparatuses.

10. A cell control apparatus installed in a battery apparatus having a battery module in which a plurality of unit battery cells are series-connected while a plurality of battery cells are series-connected electrically in each of the unit battery cells and a battery control apparatus, the cell control apparatus communicating with the battery control apparatus through a signal transmitting path having an insulating means for insulating an electrical connection,

wherein the cell control apparatus comprises

integrated circuits which are provided for each of the plurality of unit battery cells and are connected electrically to the plurality of battery cells of the associated unit battery cells;

and

a signal transmitting path, which is constructed by connecting said first control apparatuses electrically, and which transmits a signal serially between said first control apparatuses;

wherein the signal which transmits through said first transmitting path and said second transmitting path provides a plurality of areas including a synchronous field and data byte, and a serial data signal which is constructed by a plurality of signals having high levels and low levels;

wherein the plurality of integrated circuits comprises

a speed detection section for detecting the speed of the serial data signal from the signal which is written in the synchronous field of the serial data signal which is input from an additional control apparatus,

a speed detection section for detecting the speed of the serial data signal from the signal which is written in the synchronous field of the serial data signal which is input from an additional control apparatus,

a reception timing defining section for defining the reception timing for the serial data signal in accordance with the speed detected by the speed detection section, and

a signal reading section for reading in the serial data signal at the timing of the reception timing defining signal.

11. A cell control apparatus according to claim 10,

wherein the speed detection section calculates an average time of the high level and an average time of the low level in the synchronous field of the serial data signal, calculates a period of the serial data signal from the sum of the average time of the high level and the average time of the low level, and outputs the calculated period of the serial data signal to a receiving timing defining signal output section.

12. A cell control apparatus according to claim 11,

wherein the receiving timing defining signal output section outputs a receiving timing defining signal which has the same period as the period of the serial data signal output from the speed detection section, and

wherein the receiving timing defining signal is a repeating signal of high levels and low levels, and is constructed by a plurality of high levels and low levels.

13. A cell control apparatus according to claim 12,

wherein the signal reading section reads in the serial data signal at a stand-up timing of a high level signal of the receiving timing defining signal.

14. A plurality of integrated circuits, one of which is provided for each of a plurality of unit battery cells and is connected electrically to the plurality of battery cells of the associated unit battery cell, is series-connected with the other integrated circuit while a plurality of battery cells are series-connected electrically in each of the unit battery cells, and the plurality of the integrated circuits are connected serially and electrically for constructing a signal transmitting path for transmitting a serial data signal which has a plurality of areas including a synchronous field and data byte, and a serial data signal which constructed by a plurality of signals having high levels and low levels;

wherein the integrated circuit comprises

a plurality of voltage input terminals for inputting voltages of the plurality of battery cells connected electrically,

a selecting section for selecting the plurality of voltages inputted from the plurality of the voltage input terminals and outputs the selected voltages,

a voltage detecting section for detecting the voltage which is output from the selecting section,

a signal input terminal for inputting the serial data signal,

a signal output terminal for outputting the serial data signal,

a communicating section for receiving the serial data signal input from the signal input terminal,

a speed detection section for detecting the speed of the serial data signal from the signal which is written in the synchronous field of the serial data signal which is input from an additional control apparatus,

a reception timing defining section for defining the reception timing for the serial data signal in accordance with the speed detected by the speed detection section, and

a signal reading section for reading in the serial data signal at the timing of the reception timing defining signal.

15. An integrated circuit according to claim 14,

wherein the speed detection section calculates an average time of the high level and an average time of the low level in the synchronous field of the serial data signal, calculates a period of the serial data signal from the sum of the average time of the high level and the average time of the low level, and outputs the calculated period of the serial data signal to a receiving timing defining signal output section.

16. An integrated circuit according to claim 15,

wherein the receiving timing defining signal output section outputs a receiving timing defining signal which has the same period as the period of the serial data signal output from the speed detection section, and

wherein the receiving timing defining signal is a repeating signal of high levels and low levels, and is constructed by a plurality of high levels and low levels.

17. An integrated circuit according to claim 16,

wherein the signal reading section reads in the serial data signal at a stand-up timing of a high level signal of the receiving timing defining signal.