Precise control component for a substrate potential regulation circuit

• US 8,193,852 B2
• Filed: 02/19/2010
• Issued: 06/05/2012
• Est. Priority Date: 12/23/2003
• Status: Active Grant

• Current Assignee: Tien-Min Chen
• Original Assignee: Tien-Min Chen
• Inventors: Chen, Tien-Min
• Primary Examiner(s): TRA, ANH QUAN
• Application Number:
  US12/709,421
• Publication Number:
  US 20100201434A1
• Time in Patent Office: 837 Days
• Field of Search: 327/536, 327/534, 327/535
• US Class Current: 327/534
• CPC Class Codes: G05F 3/205 Substrate bias-voltage generators for static stores G11C5/146
• CPC Class Codes: H03K 2217/0018 Special modifications or use of the back gate voltage of a FET

Abstract

A control circuit for substrate potential regulation for an integrated circuit device. The control circuit includes a current source configured to generate a reference current. A variable resistor is coupled to the current source. The variable resistor is configured to receive the reference current and generate a reference voltage at a node between the current source and the variable resistor. The reference voltage controls the operation of a substrate potential regulation circuit coupled to the node.

Claims

1. A method comprising:

generating a body bias voltage;

adjusting the body bias voltage based on a voltage value representative of the body bias voltage; and

responsive to said adjusting creating an overcharge condition, shunting the body bias voltage to correct the overcharge condition, wherein said shunting includes enabling performance of said shunting responsive to the overcharge condition occurring for a number of consecutive clock cycles.

2. The method of claim 1, wherein said generating comprises:

generating a positive body bias voltage.

3. The method of claim 1, wherein said generating comprises:

generating a negative body bias voltage.

4. The method of claim 1, wherein said adjusting comprises:

generating a reference current; and

using a variable resistor, the reference current, and the body bias voltage to generate the voltage value.

5. The method of claim 4, wherein said adjusting further comprises:

comparing the voltage value with a reference voltage; and

based on said comparison, adjusting the body bias voltage.

6. The method of claim 1, wherein said shunting comprises:

discharging an excessive negative body bias voltage to a desired voltage level.

7. The method of claim 1, wherein said shunting comprises:

discharging an excessive positive body bias voltage to a desired voltage level.

8. A method comprising:

comparing a voltage value representative of a body bias voltage with a reference voltage;

adjusting the body bias voltage based on said comparing; and

responsive to said adjusting creating an overcharge condition, shunting the body bias voltage to correct the overcharge condition, wherein said shunting includes enabling performance of said shunting responsive to the overcharge condition occurring for a number of consecutive clock cycles.

9. The method of claim 8, wherein said comparing comprises:

generating a reference current.

10. The method of claim 9, wherein said comparing further comprises:

using a variable resistor, the reference current, and the body bias voltage to generate the voltage value.

11. The method of claim 8, wherein said adjusting comprises:

generating a positive body bias voltage.

12. The method of claim 8, wherein said adjusting comprises:

generating a negative body bias voltage.

13. The method of claim 8, wherein said shunting comprises:

discharging an excessive negative body bias voltage to a desired voltage level.

14. The method of claim 8, wherein said shunting comprises:

discharging an excessive positive body bias voltage to a desired voltage level.

15. A method comprising:

generating a reference current;

using the reference current to generate a voltage value representative of a body bias voltage;

adjusting the body bias voltage based on the voltage value; and

responsive to said adjusting creating an overcharge condition, shunting the body bias voltage to correct the overcharge condition, wherein said shunting includes enabling performance of said shunting responsive to the overcharge condition occurring for a number of consecutive clock cycles.

16. The method of claim 15, wherein said adjusting comprises:

comparing the voltage value with a reference voltage; and

based on said comparison, adjusting the body bias voltage.

17. The method of claim 15, wherein said adjusting comprises:

generating a positive body bias voltage.

18. The method of claim 15, wherein said adjusting comprises:

generating a negative body bias voltage.

19. The method of claim 15, wherein said shunting comprises:

discharging an excessive negative body bias voltage to a desired voltage level.

20. The method of claim 15, wherein said shunting comprises:

discharging an excessive positive body bias voltage to a desired voltage level.