Systems and methods for enhancing analog to digital conversion resolution

• US 8,193,961 B2
• Filed: 09/23/2010
• Issued: 06/05/2012
• Est. Priority Date: 09/23/2010
• Status: Expired due to Fees

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: LSI Corporation (Broadcom, Inc.)
• Inventors: Bailey, James A., McNeill, Bruce
• Primary Examiner(s): Williams, Howard
• Application Number:
  US12/889,276
• Publication Number:
  US 20120075131A1
• Time in Patent Office: 621 Days
• Field of Search: 341/118, 341/120, 341/139, 341/155
• US Class Current: 341/155
• CPC Class Codes: H03M 1/20 Increasing resolution using an n bit system to obtain n + m bits

Abstract

Various embodiments of the present invention provide systems and methods for analog to digital conversion. As an example, a circuit for converting analog signals to digital signals is disclosed. The circuit includes a variable gain amplifier circuit, an analog to digital converter circuit, and a summation circuit. The variable gain amplifier circuit is operable to apply a first gain value to an input to yield a first amplified output, and to apply a second gain value to the input to yield a second amplified output. The analog to digital converter circuit is operable to receive a derivative of the first amplified output and to provide a corresponding first digital sample, and to receive a derivative of the second amplified output and to provide a corresponding second digital sample. The summation circuit is operable to combine the first digital sample and the second digital sample.

Claims

1. A circuit for converting analog signals to digital signals, the circuit comprising:

a variable gain amplifier circuit operable to apply a first gain value to an input to yield a first amplified output, and to apply a second gain value to the input to yield a second amplified output;

an analog to digital converter circuit operable to receive a derivative of the first amplified output and to provide a corresponding first digital sample, and to receive a derivative of the second amplified output and to provide a corresponding second digital sample; and

a summation circuit operable to combine the first digital sample and the second digital sample.

2. The circuit of claim 1, wherein combining the first digital sample and the second digital sample reduces a quantization noise resulting from the analog to digital conversion circuit.

3. The circuit of claim 1, wherein the summation circuit provides an aggregated output, and wherein the aggregated output exhibits a quantization noise that is less than a quantization noise of the first digital sample.

4. The circuit of claim 1, wherein the circuit further comprises:

a controller circuit operable to switch the first gain to the second gain after the first digital sample is obtained from the analog to digital converter circuit.

5. The circuit of claim 4, wherein the summation circuit provides an aggregated output, and wherein the controller circuit is further operable to increment the gain of the variable gain amplifier through gain values in addition to the first gain and the second gain such that the quantization noise exhibited by the aggregated output is less than twenty-five percent of the least significant bit of the analog to digital converter circuit.

6. The circuit of claim 5, wherein the quantization noise exhibited by the aggregated output is less than ten percent of the least significant bit of the analog to digital converter circuit.

7. The circuit of claim 6, wherein the quantization noise exhibited by the aggregated output is less than five percent of the least significant bit of the analog to digital converter circuit.

8. The circuit of claim 1, wherein a difference between the first gain and the second gain is at least one half of the least significant bit of the analog to digital converter circuit.

9. The circuit of claim 1, wherein a quantization noise included in the first digital sample is uncorrelated to a quantization noise in the second digital sample.

10. The circuit of claim 1, wherein the circuit further comprises:

a digital output value, wherein the first digital sample and the second digital sample are provided as the digital output value when a standard operation mode is selected, wherein the summation circuit provides an aggregated output, and wherein the aggregated output is provided as the digital output value when a test operation mode is selected.

11. The circuit of claim 1, wherein the input is selected as a test input when a test operation mode is selected, and wherein the input is selected as a standard input when a standard operation mode is selected.

12. The circuit of claim 1, wherein the circuit further comprises:

an analog filter circuit operable to receive the amplified output and to provide a filtered, wherein the derivative of the first amplified output is the filtered output corresponding to the first amplified output, and wherein the derivative of the second amplified output is the filtered output corresponding to the second amplified output.

13. The circuit of claim 1, wherein the derivative of the first amplified output is the first amplified output, and wherein the second amplified output is the second amplified output.

14. The circuit of claim 1, wherein the circuit is implemented as part of an integrated circuit.

15. A method for enhanced resolution analog to digital conversion, the method comprising:

receiving an input;

providing a variable gain amplifier circuit operable to amplify the input by an amount corresponding to a gain input;

providing an analog to digital converter circuit;

applying a first gain value to the gain input to yield a first amplified output corresponding to the input;

applying a second gain value to the gain input to yield a second amplified output corresponding to the input;

performing an analog to digital conversion of a derivative of the first amplified output using the analog to digital converter circuit to yield a first digital sample;

performing an analog to digital conversion of a derivative of the second amplified output using the analog to digital converter circuit to yield a second digital sample; and

aggregating the first digital sample and the second digital sample to yield an aggregated output.

16. The method of claim 15, wherein the method further comprises:

filtering the first amplified output to yield a first filtered output, wherein the derivative of the first amplified output is the first filtered output; and

filtering the second amplified output to yield a second filtered output, wherein the derivative of the second amplified output is the second filtered output.

17. The method of claim 15, wherein aggregating the first digital sample and the second digital sample reduces a quantization noise resulting from the analog to digital conversion circuit.

18. The method of claim 15, wherein the aggregated output exhibits a quantization noise that is less than a quantization noise of the first digital sample.

19. The method of claim 15, wherein a difference between the first gain value and the second gain value is at least one half of the least significant bit of the analog to digital converter circuit.

20. The method of claim 15, wherein a quantization noise included in the first digital sample is uncorrelated to a quantization noise in the second digital sample.

21. The method of claim 15, wherein the method further comprises:

providing the aggregated output as a digital output when a test operation mode is selected; and

providing the first digital sample and the second digital sample as the digital output when a standard operation mode is selected.