Method and system for writing data to MEMS display elements

• US 8,194,056 B2
• Filed: 02/09/2006
• Issued: 06/05/2012
• Est. Priority Date: 02/09/2006
• Status: Expired due to Fees

• Current Assignee: Snaptrack Incorporated (Qualcomm, Inc.)
• Original Assignee: Qualcomm MEMS Technologies Incorporated (Qualcomm, Inc.)
• Inventors: Kothari, Manish
• Primary Examiner(s): Shalwala, Bipin
• Assistant Examiner(s): CHOWDHURY, AFROZA Y
• Application Number:
  US11/350,712
• Publication Number:
  US 20070182707A1
• Time in Patent Office: 2,308 Days
• Field of Search: 345 84- 86, 345108-111, 345/204, 356/519, 359/209, 359/291, 359/198
• US Class Current: 345/204
• CPC Class Codes: G09G 2310/06 Details of flat display driving waveforms
• CPC Class Codes: G09G 2320/0204 Compensation of DC component across the pixels in flat panels
• CPC Class Codes: G09G 3/3466 based on interferometric effect
• CPC Class Codes: Y02E 60/10 Energy storage using batteries

Abstract

Another embodiment has a method of driving a display device including an array of MEMS elements is disclosed. The MEMS elements are characterized by a preferred set of drive potential differences including preferred positive and preferred negative actuation potential differences, preferred positive and preferred negative hold potential differences, and a preferred release potential difference, where the preferred set of drive potential differences is symmetric about a voltage differing from 0V by an offset δV. Another embodiment has a reduced set of supply voltages are used, while maintaining the charge balancing effects of applying potential differences of opposite polarity without visible artifacts.

Claims

1. A method of writing data to a display device comprising a set of MEMS display elements configured as an array of rows and columns of MEMS elements, said method comprising:

generating a first voltage level, a second voltage level, a third voltage level, and a fourth voltage level to be applied to the rows and columns; and

writing display data to the array by applying no more than the first, second, third, and fourth voltage levels to the columns and rows of the array so as to apply first and second actuation potential differences, first and second hold potential differences, and first and second release potential differences, and wherein the first and second hold potential differences are of opposite polarity and are symmetric about a non-zero offset δ

V,

wherein the MEMS elements are characterized by a preferred set of drive potential differences comprising preferred positive and preferred negative actuation potential differences, preferred positive and preferred negative hold potential differences, and a preferred release potential difference, wherein the preferred set of drive potential differences is symmetric about the non-zero offset δ

V and wherein drive potential differences are applied to each MEMS element as a difference between a column voltage and a row voltage, and

wherein no more than two of the first, second, third, and fourth voltage levels are applied to the columns and no more than three of the first, second, third, and fourth voltage levels are applied to the rows, and wherein the no more than three voltage levels voltages and the no more than two voltage levels share one common voltage level.

2. The method of claim 1, wherein said first hold potential is a positive polarity such that the column is at a higher potential than the row, and wherein said second hold potential is a negative polarity such that the row is at a higher potential than the column.

3. The method of claim 1, wherein δ

V is a positive value.

4. The method of claim 1, wherein δ

V is a negative value.

5. The method of claim 1, wherein one of the no more than three voltage levels three voltages is shifted from one of the no more than two voltage levels by about 2δ

V.

6. The method of claim 1;

wherein the common voltage is about 0V.

8. The method of claim 1, wherein the first and second actuation potential differences are symmetric about the offset voltage δ

V.

9. The method of claim 1, wherein the first and second release potential differences are symmetric about the offset voltage δ

V.

7. The method of claim , wherein the common voltage is about 5V or more.

10. A microelectromechanical system (MEMS) display device comprising:

an array of rows and columns of MEMS elements, wherein the MEMS elements are characterized by a preferred set of drive potential differences comprising preferred positive and preferred negative actuation potential differences, preferred positive and preferred negative hold potential differences, and a preferred release potential difference, wherein the preferred set of drive potential differences is symmetric about a voltage differing from 0V by a nonzero offset δ

V; and

an array driver configured to write display data to the array by applying no more than first, second, third, and fourth voltage levels to the rows and columns of the array so as to apply first and second actuation potential differences, first and second hold potential differences, and first and second release potential differences, wherein first and second hold potentials are of opposite polarity and are symmetric about the non-zero offset δ

V,

wherein the array controller is configured to apply no more than two of the first, second, third, and fourth voltage levels are applied to the columns and no more than three of the first, second, third, and fourth voltage levels are applied to the rows, and wherein the no more than three voltage levels voltages and the no more than two voltage levels share one common voltage level.

11. The device of claim 10, wherein said first hold potential is a positive polarity such that the column is at a higher potential than the row, and wherein said second hold potential is a negative polarity such that the row is at a higher potential than the column.

12. The device of claim 10, wherein 8V is a positive value.

13. The device of claim 10, wherein 6V is a negative value.

14. The device of claim 10, wherein one of no more than three voltage levels is shifted from one of the no more than two voltage levels by about 2δ

V.

15. The device of claim 10, wherein the common voltage is about 0 V.

16. The device of claim 10, wherein the common voltage is about 5V or more.

17. The device of claim 10, wherein the first and second actuation potential differences are symmetric about the offset voltage δ

V.

18. The device of claim 10, wherein the first and second release potential differences are symmetric about the offset voltage δ

V.

19. The device of claim 10, further comprising:

a processor that is configured to communicate with said display, said processor being configured to process image data; and

a memory device that is configured to communicate with said processor.

20. The device of claim 19, further comprising a controller configured to send at least a portion of the image data to the driver circuit.

21. The device of claim 19, further comprising an image source module configured to send said image data to said processor.

22. The device of claim 21, wherein the image source module comprises at least one of a receiver, transceiver, and transmitter.

23. The device of claim 19, further comprising an input device configured to receive input data and to communicate said input data to said processor.

24. A method of driving a display device comprising a set of MEMS display elements configured as an array of rows and columns of MEMS elements, the method comprising:

generating a first voltage level, a second voltage level, a third voltage level, and a fourth voltage level to be applied to the rows and columns;

writing display data to the array by applying no more than the first, second, third, and fourth voltage levels to the columns and rows of the array so as to apply first and second actuation potential differences, first and second hold potential differences, and first and second release potential differences, and wherein at least one of the first and second actuation potentials, the first and second hold potentials, and the first and second release potentials are of opposite polarity and are symmetric about a voltage differing from 0V by a nonzero offset δ

V,

wherein said MEMS elements are characterized by a preferred set of drive potential differences comprising preferred positive and preferred negative actuation potential differences, preferred positive and preferred negative hold potential differences, and a preferred release potential difference, wherein the preferred set of drive potential differences is symmetric about the offset voltage δ

V and wherein drive potential differences are applied to each MEMS element as a difference between a column voltage and a row voltage, and

wherein no more than two of the first, second, third, and fourth voltage levels are applied to the columns and no more than three of the first, second, third, and fourth voltage levels are applied to the rows, and wherein the no more than three voltage levels voltages and the no more than two voltage levels share one common voltage level.

25. The method of claim 24, wherein said first hold potential is a positive polarity such that the column is at a higher potential than the row, and wherein said second hold potential is a negative polarity such that the row is at a higher potential than the column.

26. The method of claim 24, wherein δ

V is a positive value.

27. The method of claim 24, wherein δ

V is a negative value.

28. The method of claim 24, wherein each of the first and second actuation potentials, the first and second hold potentials, and the first and second hold potentials are of opposite polarity and are symmetric about the offset voltage δ

V.

29. The method of claim 24, wherein the light modulation characteristics of each MEMS display element when driven with a positive polarity potential is substantially identical to the light modulation characteristics when driven with a negative polarity potential.

30. The method of claim 24, wherein one of the first, second, third, and fourth voltage levels is substantially equal to 0V.

31. The method of claim 30, wherein each of said first and second actuation potential differences, first and second hold potential differences, first and second release potential differences, preferred positive and preferred negative actuation potential differences, preferred positive and preferred negative hold potential differences, and preferred release potential difference comprises a difference between a voltage applied to a column electrode of a MEMS display element in the array and a voltage applied to a row electrode of the MEMS display element.

32. A microelectromechanical system (MEMS) display device comprising:

means for displaying rows and columns of image data, wherein said means are characterized by a preferred set of drive potential differences comprising preferred positive and preferred negative actuation potential differences, preferred positive and preferred negative hold potential differences, and a preferred release potential difference, wherein the preferred set of drive potential differences is symmetric about a voltage differing from 0V by a nonzero offset δ

V; and

means for writing image data to the means for displaying by applying no more than first, second, third, and fourth voltage levels to the rows and columns of the array so as to apply first and second actuation potential differences, first and second hold potential differences, and first and second release potential differences, wherein first and second hold potentials are of opposite polarity,

wherein no more than two of the first, second, third, and fourth voltage levels are applied to the columns and no more than three of the first, second, third, and fourth voltage levels are applied to the rows, and wherein the no more than three voltage levels voltages and the no more than two voltage levels share one common voltage level.

33. The device of claim 32, wherein said means for displaying comprises an array of MEMS elements configured as interferometric modulators.

34. The device of claim 33, wherein said means for writing image data comprises an array driver circuit.