nvSRAM having variable magnetic resistors

• US 8,194,438 B2
• Filed: 02/12/2009
• Issued: 06/05/2012
• Est. Priority Date: 02/12/2009
• Status: Expired due to Fees

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Inventors: Ahn, Yongchul, Khoueir, Antoine, Lu, Yong, Liu, Hongyue
• Primary Examiner(s): Nguyen, Tuan T
• Assistant Examiner(s): REIDLINGER, RONALD LANCE
• Application Number:
  US12/370,164
• Publication Number:
  US 20100202191A1
• Time in Patent Office: 1,209 Days
• Field of Search: 365/154, 365/156, 365/185.08, 365/148, 365/158, 365/163, 365/171, 365/173
• US Class Current: 365/158
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: G11C 14/0081 and the nonvolatile element is a magnetic RAM [MRAM] element or ferromagnetic cell

Abstract

Non-volatile static random access memory (nvSRAM) that has a six transistor static random access memory (6T SRAM) cell electrically connected to a non-volatile random access memory (nvRAM) cell. The nvRAM cell has first and second variable magnetic resistors and first, second and third transistors.

Claims

1. A non-volatile static random access memory (nvSRAM) comprising:

a six transistor static random access memory (6T SRAM) cell; and

a non-volatile random access memory (nvRAM) cell comprising a first stack and a second stack in parallel, the first stack comprising a first variable magnetic resistor and a first transistor, the second stack comprising a second variable magnetic resistor and a second transistor, the first stack and the second stack each in series with a third transistor

the 6T SRAM cell electrically connected to the nvRAM cell, wherein the first and second variable magnetic resistors are spin-torque magnetic tunnel junctions comprising a free layer, a pinned layer, and a tunneling layer therebetween.

2. The nvSRAM of claim 1 wherein the first stack and the second stack are each electrically connected between the SRAM cell and the third transistor.

3. The nvSRAM of claim 1 wherein the first and second transistors are electrically connected to a first voltage source to enable the first and second transistors, the third transistor is connected to a second voltage source to enable the third transistor, and the third transistor has a source/drain terminal that is electrically connected to a third voltage source.

4. The nvSRAM of claim 1 wherein the first and second stacks are arranged with the first and second variable magnetic resistors electrically between the first and second transistors, respectively, and the third transistor.

5. A non-volatile static random access memory (nvSRAM) comprising:

a six transistor static random access memory (6T SRAM) cell; and

a non-volatile random access memory (nvRAM) cell comprising a first stack and a second stack connected in parallel to the 6T SRAM cell, and a third transistor connected in series to each of the first stack and the second stack, the stacks positioned electrically between the 6T SRAM cell and the third transistor, wherein the first stack comprises a spin-torque magnetic tunnel junction comprising a free layer, a pinned layer, and a tunneling layer therebetween and a first transistor, and the second stack comprises a spin-torque magnetic tunnel junction comprising a free layer, a pinned layer, and a tunneling layer therebetween and a second transistor.

6. The nvSRAM of claim 5 wherein:

the first transistor and the second transistor are electrically connected to a first voltage source to enable the first and second transistors,

the third transistor is connected to a second voltage source to enable the third transistor, and

the third transistor has a source/drain terminal that is electrically connected to a third voltage source.

7. The nvSRAM of claim 5 wherein the first and second stacks are arranged with the first and second variable magnetic resistors electrically between the first and second transistors, respectively, and the third transistor.