Methods and systems for using electrical information for a device being fabricated on a wafer to perform one or more defect-related functions

• US 8,194,968 B2
• Filed: 01/07/2008
• Issued: 06/05/2012
• Est. Priority Date: 01/05/2007
• Status: Active Grant

• Current Assignee: KLA-Tencor Corporation
• Original Assignee: KLA-Tencor Corporation
• Inventors: Park, Allen, Rose, Peter, Chang, Ellis, Duffy, Brian, McCord, Mark, Abbott, Gordon
• Primary Examiner(s): NGUYEN, TU T
• Application Number:
  US11/970,294
• Publication Number:
  US 20080167829A1
• Time in Patent Office: 1,611 Days
• Field of Search: None
• US Class Current: 382/145
• CPC Class Codes: G01N 21/8851 Scan or image signal processing specially adapted therefor, e.g. for scan signal adjustment, for detecting different kinds of defects, for compensating for structures, markings, edges G01N21/8806 and G01N21/93 - G01N21/95692 take precedence; optical measurement of dimensions G01B11/00; optical scanning G02B26/10; image transformation G06T3/00; computerised image enhancement G06T5/00; image processing per se for flaw detection G06T7/0002
• CPC Class Codes: G01N 21/956 Inspecting patterns on the surface of objects contactless testing of electronic circuits G01R31/308; testing currency G07D; manufacturing processes per se of semiconductor devices implementing a measuring step H01L22/10
• CPC Class Codes: G01R 31/2894 Aspects of quality control [QC] G01R31/31718 takes precedence; program control for QC G05B19/41875
• CPC Class Codes: G06T 2207/30148 Semiconductor; IC; Wafer
• CPC Class Codes: G06T 7/0004 Industrial image inspection

Abstract

Various methods and systems for using electrical information for a device being fabricated on a wafer to perform one or more defect-related functions are provided. One computer-implemented method includes using electrical information for a device being fabricated on a wafer to perform one or more defect-related functions. The one or more defect-related functions include one or more post-mask, defect-related functions.

Claims

1. A computer-implemented method, comprising:

generating electrical information for a device being fabricated on a wafer by processing design data for the device, wherein the design data cormprises physical layout information, three-dimensional structure information, netlist information, or some combination thereof; and

using the electrical information to perform one or more defect-related functions, wherein the one or more defect-related functions comprise one or more post-mask, defect-related functions, wherein the one or more defect-related functions further comprise using the electrical information and defect information generated by a defect review tool to determine electrical effects on the device due to defects detected on the wafer and using the electrical effects to determine a classification or ranking for the defects and wherein said generating and said using the electrical information are performed using a computer system.

2. The method of claim 1, wherein the electrical information comprises critical path information.

3. The method of claim 1, wherein the one or more defect-related functions further comprise determining performance of the device using defect inspection data acquired for the wafer and the electrical information.

4. The method of claim 1, wherein the one or more defect-related functions further comprise using the electrical information and defect inspection data acquired for the wafer in real time to determine performance of the device.

5. The method of claim 1, wherein the one or more defect-related functions further comprise determining potential yield impact of defects on the device using defect inspection data acquired for the wafer and the electrical information.

6. The method of claim 1, wherein the one or more defect-related functions further comprise using the electrical information and defect inspection data acquired for the wafer in real time to determine potential yield impact of defects on the device.

7. The method of claim 1, wherein the one or more defect-related functions further comprise determining electrical relevancy of defects detected on the wafer.

8. The method of claim 1, wherein the one or more defect-related functions further comprise determining timing delay of the device due to defects detected on the wafer using defect inspection data acquired for the wafer and the electrical information.

9. The method of claim 1, wherein the one or more defect-related functions further comprise using the electrical information and defect inspection data acquired for the wafer in real time to determine timing delay of the device due to defects detected on the wafer.

10. The method of claim 1, wherein the one or more defect-related functions further comprise determining power leakage of the device due to defects detected on the wafer using defect inspection data acquired for the wafer and the electrical information.

11. The method of claim 1, wherein the one or more defect-related functions further comprise using the electrical information and defect inspection data acquired for the wafer in real time to determine power leakage of the device due to defects detected on the wafer.

12. The method of claim 1, wherein the one or more defect-related functions further comprise determining resistance-capacitance variation of the device due to defects detected on the wafer using the electrical information and defect inspection data acquired for the wafer.

13. The method of claim 1, wherein the one or more defect-related functions further comprise using the electrical information and defect inspection data acquired for the wafer in real time to determine resistance-capacitance variation of the device due to defects detected on the wafer.

14. The method of claim 1, wherein the electrical information comprises critical path information, and wherein the critical path information is acquired from netlist information for the device.

15. The method of claim 1, wherein the one or more defect-related functions further comprise identifying critical defects on the wafer.

16. The method of claim 1, wherein the one or more defect-related functions further comprise separating defects detected in areas of the wafer corresponding to electrically sensitive areas of the device from other defects detected on the wafer.

17. The method of claim 1, wherein the one or more defect-related functions further comprise identifying one or more inspection areas on the wafer.

18. The method of claim 1, wherein the one or more defect-related functions further comprise identifying critical metrology sites on the wafer.

19. The method of claim 1, wherein the one or more defect-related functions further comprise separating metrology variations measured in areas of the wafer corresponding to electrically sensitive areas of the device from other measured metrology variations.

20. The method of claim 1, wherein the one or more defect-related functions further comprise determining electrical relevancy of metrology data acquired for the wafer.

21. The method of claim 1, wherein the electrical information comprises critical path information, and wherein the critical path information is generated by an electronic design automation tool.

22. The method of claim 1, wherein the electrical information comprises critical path information, and wherein the one or more defect-related functions further comprise defect sampling in which only defects on the wafer located on or near critical paths in the device are selected for review.

23. The method of claim 1, wherein the electrical information comprises critical path information, and wherein the one or more defect-related functions further comprise overlaying the critical path information with defect inspection data acquired for the wafer and using results of said overlaying to identify critical defects on the wafer for review.

24. The method of claim 1, further comprising using optimized design data for the device to describe defects detected on the wafer by error budget.

25. The method of claim 1, further comprising evaluating optimization of design data for the device by searching the design data for patterns of interest, wherein the patterns of interest comprise patterns corrected and not corrected by the optimization, and comparing a failure rate of corrected and non-corrected patterns in the design data for the device.

26. The method of claim 1, wherein the one or more defect-related functions further comprise creating a systematic pareto by critical and non-critical areas of the device to identify critical and non-critical systematic defects on the wafer.

27. The method of claim 1, wherein the electrical information comprises critical. path information, and wherein the one or more defect-related functions further comprise separating systematic defects detected on the wafer located in critical paths of the device from systematic defects detected on the wafer located in non-critical paths of the device.

28. The method of claim 1, wherein the electrical information comprises critical path information, and wherein the one or more defect-related functions further comprise separating random defects detected on the wafer located in critical paths of the device from random defects detected on the wafer located in non-critical paths of the device.

29. The method of claim 1, wherein the one or more defect-related functions are performed for defects detected on the wafer by bright field inspection.

30. The method of claim 1, wherein the electrical information comprises critical path information, and wherein the one or more defect-related functions further comprise using the critical path information to setup a metrology process for the wafer such that changes in critical dimensions of features of the device on the wafer are measured and can be correlated to parametric performance of the device.

31. The method of claim 1, wherein the one or more defect-related functions further comprise inspection of the wafer.

32. The method of claim 1, wherein the one or more defect-related functions further comprise defect review of the wafer.

33. The method of claim 1, wherein the one or more defect-related functions further comprise metrology of the wafer.

34. The method of claim 1, wherein the electrical information comprises netlist data.

35. The method of claim 1, wherein the electrical information comprises netlist data provided to an inspection system used to inspect the wafer.

36. The method of claim 1, wherein the electrical information comprises electrical. circuit information.

37. The method of claim 1, wherein the one or more defect-related functions further comprise targeted electron beam-based inspection of the wafer.

38. The method of claim 1, wherein the one or more defect-related functions further comprise targeted binning of defects detected by electron beam-based inspection of the wafer.

39. The method of claim 1, wherein the one or more defect-related functions further comprise automatic care area generation for inspection of the wafer.

40. The method of claim 1, wherein the one or more defect-related functions further comprise automatic setup of inspection care areas for inspection of the wafer based on circuit electrical function of the device.

41. The method of claim 1, wherein the one or more defect-related functions further comprise binning defects detected on the wafer based on electrical activity.

42. The method of claim 1, wherein the one or more defect-related functions further comprise binning defects detected on the wafer based on electrical environment of the defects.

43. The method of claim 1, wherein the one or more defect-related functions further comprise binning defects detected on the wafer based on connectivity of features of the device such that defects having different connectivity are binned into different groups of defects.

44. The method of claim 1, wherein the one or more defect-related functions further comprise binning defects detected on the wafer based on connectivity of features of the device such that nuisance defects are binned into a group different than one or more groups of non-nuisance defects.

45. The method of claim 1, wherein the one or more defect-related functions further comprise determining if multiple electrically defective nodes are connected and binning the multiple electrically defective nodes as a single defect if the multiple electrically defective nodes are connected.

46. The method of claim 1, wherein the electrical information comprises critical timing paths in the device extracted from netlist data, and wherein the one or more defect-related functions further comprise setup of targeted care areas for inspection of the wafer.

47. The method of claim 1, wherein the one or more defect-related functions further comprise using electrical connectivity information for the device to predict voltage contrast gray levels of images acquired during die-to-reference, electron beam-based inspection of the wafer and using the predicted voltage contrast gray levels to match the images to rendered images of design data for the device stored in a data structure.

48. The method of claim 1, wherein the one or more defect-related functions further comprise rendering images of design data for the device for die-to-reference, electron beam-based inspection of the wafer and storing the rendered images in a data structure.

49. The method of claim 1, wherein the electrical information comprises electrical design information for the device being fabricated on the wafer.

50. The method of claim 1, wherein the electrical information comprises electrical design analysis.

51. The method of claim 1, wherein the one or more defect-related functions further comprise assisting defect review of the wafer in real time.

52. The method of claim 1, wherein the one or more defect-related functions further comprise assisting defect review of the wafer by assisting in defect classification.

53. The method of claim 1, wherein the one or more defect-related functions further comprise assisting defect review of the wafer by assisting sampling of defects for the defect review.

54. The method of claim 1, wherein the one or more defect-related functions further comprise making one or more decisions in real time during defect review of a defect location on the wafer.

55. The method of claim 1, wherein the one or more defect-related functions further comprise making one or more decisions in real time during defect review of a defect location on the wafer, and wherein the defect location is determined based on inspection of a reticle used to print a portion of the device on the wafer.

56. The method of claim 1. wherein the one or more defect-related functions further comprise making one or more decisions in real time during defect review of a defect location on the wafer, and wherein the defect location is determined based on design analysis of the device performed to determine critical hot spots for defect detection or monitoring.

57. The method of claim 1, wherein the one or more defect-related functions further comprise determining, in real time during defect review of a defect location on the wafer, if a defect at the defect location is electrically relevant to the device.

58. The method of claim 1, wherein the one or more defect-related functions further comprise determining, in real time during defect review of a defect location on the wafer, if additional spot inspections of other parts of the device in the same electrical path as a defect at the defect location are to be performed to assist in determining electrical relevance of the defect.

59. The method of claim 1, wherein the one or more defect-related functions further comprise determining, in real time during defect review of a defect location on the wafer, if additional spot inspections of other parts of the device in the same electrical path and layer as a defect at the defect location are to be performed to assist in determining electrical relevance of the defect.

60. The method of claim 1, wherein the one or more defect-related functions further comprise determining, in real time during defect review of a defect location on the wafer, if additional spot inspections of other parts of the device in the same electrical path as a defect at the defect location and on layers other than a layer associated with the defect are to be performed to assist in determining electrical relevance of the defect.

61. The method of claim 1, wherein the one or more defect-related functions further comprise binning, in real time during defect review, reviewed defects on the wafer in a pareto chart based on the electrical information.

62. The method of claim 1. wherein the one or more defect-related functions further comprise binning, in real time during defect review, reviewed defects on the wafer in a pareto chart based on the electrical information, wherein the electrical information comprises analysis of the design, and determining, in real time during the defect review, an electrical-based ranking of an effect on yield of one or more of the reviewed defects.

63. The method of claim 1, wherein the one or more defect-related functions further comprise defect classification.

64. The method of claim 1, wherein the one or more defect-related functions further comprise identifying electrically critical hot spots in the device.

65. The method of claim 1, wherein the one or more defect-related functions further comprise identifying electrically critical hot spots in the device using information from a tool configured to define a process window for fabrication of the device on the wafer.

66. The method of claim 1, wherein the one or more defect-related functions further comprise identifying electrically critical hot spots in the device using information from a tool configured to define a process window for fabrication of the device on the wafer, and wherein the electrically critical hot spots comprise locations at an edge of the process window for the device and critical to electrical performance of the device.

67. The method of claim 1, wherein the one or more defect-related functions further comprise identifying electrically critical hot spots in the device and selecting the electrically critical hot spots for inspection, monitoring, or some combination thereof during defect review performed on the wafer.

68. The method of claim 1, further comprising generating the electrical information by processing, design data for the device, wherein the design data comprises physical layout information, three-dimensional structure information, netlist information, or some combination thereof, and wherein the one or more defect-related functions further comprise determining a classification or ranking in real time for a defect on the wafer reviewed by a defect review tool.

69. The method of claim 1, further comprising prior to defect review, generating the electrical information using design data for the device to determine locations of the most critical areas of the device in terms of electrical performance and storing the locations in a storage medium accessible by a review tool.

70. The method of claim 1, further comprising prior to defect review, generating the electrical information using design data for the device to determine locations of the most critical areas of the device in terms of electrical performance and storing the locations in a storage medium accessible by a review tool, wherein the one or more defect-related functions further comprise using the locations to monitor the locations for defectivity.

71. The method of claim 1, wherein the one or more defect-related functions further comprise using electrical critical dimension margins for defect classification.

72. The method of claim 1, wherein the one or more defect-related functions further comprise real time detect classification based on electrical performance effects on the device due to defects detected on the wafer and sampling the defects for review based on electrical design data.

73. The method of claim 1, wherein the one or more defect-related functions further comprise determining an effect of a defect on the wafer on electrical performance of the device.

74. The method of claim 1, wherein the one or more defect-related functions further comprise using electrically critical hot spots in the device to perform defect monitoring.

75. The method of claim 1, wherein the one or more defect-related functions further comprise using the electrical information to determine additional device sampling based on a defect detected on the wafer.

76. The method of claim 1, wherein the one or more defect-related functions further comprise, during inspection of the wafer, classifying defects detected on the wafer into different memory-specific failure modes.

77. The method of claim 1, wherein the one or more defect-related functions further comprise classifying defects detected on the wafer into different memory-specific failure modes, and wherein the method further comprises altering a memory redundancy design optimization strategy based on results of classifying the defects.

78. The method of claim 1, wherein the one or more defect-related functions further comprise classifying defects detected on the wafer into different memory-specific failure modes, and wherein the method further comprises determining testing to be performed on the wafer based on results of classifying the defects.

79. The method of claim 1, wherein the one or more defect-related functions further comprise inline memory failure mode classification performed based on defect inspection data and design context surrounding defects detected on the wafer.

80. The method of claim 1, wherein the one or more defect-related functions further comprise inline memory failure mode classification, and wherein the inline memory failure mode classification comprises registering patterns of interest in the device, performing defect inspection, retrieving GDS clips for every defect detected by the defect inspection, classifying the defects based on GDS matching with known patterns of interest, and based on defect location and defect size, classifying the defects into different memory failure modes.

81. The method of claim 1, wherein the one or more defect-related functions further comprise separating bit failure from word-line or bit-line failure using patterns of interest.

82. The method of claim 1, wherein the one or more defect-related functions further comprise separating single bit failure from double-hit failure based on defect size.

83. The method of claim 1, wherein the one or more defect-related functions further comprise inline memory failure mode classification, and wherein the inline memory failure mode classification comprises associating a defect to a layer of the device and location of cells in the device to determine the failure mode of the defect.

84. A non-transitory computer-readable medium, comprising program instructions executable on a computer system for performing a computer-implemented method, wherein the computer-implemented method comprises;

generating electrical information for a device being fabricated on a wafer by processing design data for the device wherein the design data comprises physical layout information, three-dimensional structure information, netlist information, or some combination thereof; and

using the electrical information to perform one or more defect-related functions, wherein the one or more defect-related functions comprise one or more post-mask, defect-related functions, and wherein the one or more defect-related functions further comprise using the electrical information and defect information generated by a defect review tool to determine electrical effects on the device due to defects detected on the wafer and using the electrical effects to determine a classification or ranking for the defects.

85. A system configured to perform a computer-implemented method, comprising a computer system configured to perform the computer-implemented method, wherein the computer-implemented method comprises;

generating electrical information for a device bein fabricated on a wafer by processing design data for the device, wherein the design data comprises physical layout information three-dimensional structure information netlist information, or some combination thereof; and

using the electrical information to perform one or more defect-related functions, wherein the one or more defect-related functions comprise one or more post-mask, defect-related functions, and wherein the one or more defect-related functions further comprise using the electrical information and defect information generated by a defect review tool to determine electrical effects on the device due to defects detected on the wafer and using the electrical effects to determine a classification or ranking for the defects.