I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures

• US 8,195,856 B2
• Filed: 07/21/2010
• Issued: 06/05/2012
• Est. Priority Date: 12/20/1996
• Status: Expired due to Fees

• Current Assignee: Scientia Sol Mentis AG (PACT XPP Schweiz AG)
• Original Assignee: Martin Vorbach, Münch, Robert
• Inventors: Münch, Robert, Vorbach, Martin
• Primary Examiner(s): AUVE, GLENN ALLEN
• Application Number:
  US12/840,742
• Publication Number:
  US 20100287318A1
• Time in Patent Office: 685 Days
• Field of Search: 710/100, 710/107, 710/305, 711/118, 711/126, 711/154, 712/10, 712/11, 712/16, 712/17, 712 32- 36
• US Class Current: 710/100
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers

Abstract

A general bus system is provided which combines a number of internal lines and leads them as a bundle to the terminals. The bus system control is predefined and does not require any influence by the programmer. Any number of memories, peripherals or other units can be connected to the bus system (for cascading).

Claims

1. A data processor chip comprising:

a plurality of programmable data processing arrangements;

a segmented bus system including a plurality of segments that are adapted for simultaneous transmission on at least two of the plurality of segments, and that are adapted for interconnecting the plurality of programmable data processing arrangements;

at least one data cache arrangement that;

is adapted for connection to the plurality of programmable data processing arrangements via at least a subset of the plurality of segments; and

includes an arbiter adapted to select, for each of a plurality of data transmissions, at least one respective one of the plurality of segments for a respective connection to one or more of the plurality of programmable data processing arrangements; and

at least one permanently implemented memory interface unit that is adapted for transferring data between the at least one data cache and;

a higher level memory.

2. The data processor chip according to claim 1, wherein the higher level memory is a Synchronous DRAM memory.

3. The data processor chip according to claim 1, wherein the higher level memory is a RAMBUS memory.

4. The data processor chip according to claim 1, wherein the higher level memory is a synchronous memory.

5. The data processor chip according to claim 4, wherein the synchronous memory is a Synchronous DRAM memory.

6. The data processor chip according to claim 4, wherein the synchronous memory is a RAMBUS memory.