Information handling system with immediate scheduling of load operations in a dual-bank cache with dual dispatch into write/read data flow

• US 8,195,880 B2
• Filed: 04/15/2009
• Issued: 06/05/2012
• Est. Priority Date: 04/15/2009
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Gai, Sanjeev, Guthrie, Guy Lynn, Shen, Hugh, Starke, William John
• Primary Examiner(s): Luu, Pho M
• Assistant Examiner(s): Bui, Thao
• Application Number:
  US12/424,255
• Publication Number:
  US 20100268887A1
• Time in Patent Office: 1,147 Days
• Field of Search: 711/120, 711/127, 711/130, 711/131
• US Class Current: 711/120
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/0897 with two or more cache hierarchy levels with multilevel cache hierarchies G06F12/0811

Abstract

An information handling system (IHS) includes a processor with a cache memory system. The processor includes a processor core with an L1 cache memory that couples to an L2 cache memory. The processor includes an arbitration mechanism that controls load and store requests to the L2 cache memory. The arbitration mechanism includes control logic that enables a load request to interrupt a store request that the L2 cache memory is currently servicing. The L2 cache memory includes dual data banks so that one bank may perform a load operation while the other bank performs a store operation. The cache system provides dual dispatch points into the data flow to the dual cache banks of the L2 cache memory.

Claims

1. A method comprising:

sending, by a processor element, a plurality of requests for memory operations to a cache memory, the cache memory including first and second cache banks, the memory operations including load operations and store operations, each load and store operation exhibiting a respective size requirement;

arbitrating, by an arbitration mechanism, among the plurality of requests for memory operations to select a particular load operation and a particular store operation for access to the cache memory;

arbitrating, by the arbitration mechanism, in a first arbitration stage among the load operation requests in the plurality of requests for memory operations, to provide the particular load operation for access to the cache memory;

arbitrating, by the arbitration mechanism, in the first arbitration stage among the store requests, to provide the particular store operation for access to the cache memory;

arbitrating, by the arbitration mechanism, in the first arbitration stage among read claim state machine requests, cast out state machine requests and snoop requests to determine a cache arbiter arbitration result;

arbitrating, by the arbitration mechanism, in a second arbitration stage that includes first and second arbiters that operate in parallel to provide particular first and second store instructions to a third arbitration stage;

commencing, by the arbitration mechanism, the particular load operation on the first cache bank during a first cache cycle;

commencing, by the arbitration mechanism, the particular store operation on the second cache bank during the first cache cycle such that both the particular load operation and the particular store operation commence during the same first cache cycle; and

performing, by the first and second cache banks, the particular load operation and the particular store operation simultaneously.

2. The method of claim 1, further comprising interrupting with a load operation, by a control logic, the particular store operation that is in progress in one of the first and second cache banks.

3. The method of claim 1, further comprising:

determining, by a control logic, the respective size requirements of the store operations and the load operations in the plurality of requests;

performing a first cache memory access, by the cache memory, in response to a load operation request, the first cache memory access being limited in size to the size requirement for the load operation determined by the control logic; and

performing a second cache memory access, by the cache memory, in response to a store operation request, the second cache memory access being limited in size to the size requirement for the store operation determined by the control logic.

4. The method of claim 1, wherein the third arbitration stage includes third and fourth arbiters that are responsive to the first and second arbiters, respectively, of the second stage, the third and fourth arbiters of the third stage also being responsive to the particular load instruction from the first stage, the method further comprising:

arbitrating, by the arbitration mechanism, in the third arbitration stage wherein the third and fourth arbiters operate in parallel to provide the particular load operation to the first cache bank and to provide one of the particular first and second store operations to the second bank for simultaneous access to the cache memory.

5. The method of claim 1, wherein the cache memory is an L2 cache memory.

6. The method of claim 1, wherein the processor element is a processor core that includes an L1 cache memory.

7. A cache memory system comprising:

a processor element; and

a cache memory, coupled to the processor element, that receives a plurality of requests for memory operations, the cache memory including first and second cache banks, the memory operations including load operations and store operations, each load and store operation exhibiting a respective size requirement, the cache memory including an arbitration mechanism that arbitrates among the plurality of requests for memory operations to select a particular load operation and a particular store operation for access to the cache memory, wherein the arbitration mechanism comprises a first arbitration stage that arbitrates among the load operation requests in the plurality of requests for memory operations, to provide the particular load operation for access to the cache memory, the first arbitration stage arbitrating among store requests to provide a selected store operation for access to the cache memory, the first arbitration stage arbitrating among read claim state machine requests, cast out state machine requests and snoop requests to determine a cache arbiter arbitration result, wherein the arbitration mechanism further comprises a second arbitration stage, coupled to the first arbitration stage, that includes first and second arbiters that operate in parallel to provide particular first and second store instructions to a third arbitration stage, and wherein the arbitration mechanism commences the particular load operation on the first cache bank during a first cache cycle and commences the particular store operation on the second cache bank during the first cache cycle such that both the particular load operation and the particular store operation commence during the same first cache cycle, the first and second cache banks performing the particular load operation and the particular store operation simultaneously.

8. The cache memory system of claim 7, further comprising interrupting with a load operation, by a control logic in the cache memory, the particular store operation that is in progress in one of the first and second cache banks.

9. The cache memory system of claim 7, further wherein a control logic determines the respective size requirements of the store operations and the load operations in the plurality of requests, wherein the cache memory performs a first cache memory access in response to a load operation request, the first cache memory access being limited in size to the size requirement for the load operation determined by the control logic, wherein the cache memory performs a second cache memory access in response to a store operation request, the second cache memory access being limited in size to the size requirement for the store operation determined by the control logic.

10. The cache memory system of claim 7, wherein the second stage arbitration result is the particular store operation, the arbitration mechanism further comprising:

a third arbitration stage, coupled to the second arbitration stage, that includes third and fourth arbiters that are responsive to the first and second arbiters, respectively, of the second stage, the third and fourth arbiters of the third stage also being responsive to the particular load instruction from the first stage, wherein the third and fourth arbiters operate in parallel to provide the particular load operation to the first cache bank and to provide one of the particular first and second store operations to the second bank for access to the cache memory simultaneously with the particular load operation.

11. The cache memory system of claim 7, wherein the cache memory is an L2 cache memory.

12. The cache memory system of claim 7, wherein the processor element is a processor core that includes an L1 cache memory.

13. A information handling system (IHS) comprising:

a processor element;

a cache memory, coupled to the processor element, that receives a plurality of requests for memory operations, the cache memory including first and second cache banks, the operations including load operations and store operations, each load and store operation exhibiting a respective size requirement, the cache memory including an arbitration mechanism that arbitrates among the plurality of requests for memory operations to select a particular load operation and a particular store operation for access to the cache memory, wherein the arbitration mechanism comprises a first arbitration stage that arbitrates among the load operation requests in the plurality of requests for memory operations, to provide the particular load operation for access to the cache memory, the first arbitration stage arbitrating among store requests to provide a selected store operation for access to the cache memory, the first arbitration stage arbitrating among read claim state machine requests, cast out state machine requests and snoop requests to determine a cache arbiter arbitration result, wherein the arbitration mechanism further comprises a second arbitration stage, coupled to the first arbitration stage, that includes first and second arbiters that operate in parallel to provide particular first and second store instructions to a third arbitration stage; and

wherein the arbitration mechanism commences the particular load operation on the first cache bank during a first cache cycle and commences the particular store operation oh the second cache bank during the first cache cycle such that both the particular load operation and the particular store operation commence during the same first cache cycle, the first and second cache banks performing the particular load operation and the particular store operation substantially simultaneously; and

a system memory coupled to the cache memory.

14. The IHS of claim 13, wherein the arbitration mechanism further comprises:

a third arbitration stage, coupled to the second arbitration stage, that includes third and fourth arbiters that are responsive to the first and second arbiters, respectively, of the second stage, the third and fourth arbiters of the third stage also being responsive to the particular load instruction from the first stage, wherein the third and fourth arbiters operate in parallel to provide the particular load operation to the first cache bank and to provide one of the particular first and second store operations to the second bank for access to the cache memory simultaneously with the particular load operation.

15. The IHS of claim 13, further comprising interrupting with a load operation, by a control logic in the cache memory, the particular store operation that is in progress in one of the first and second cache banks.

16. The IHS of claim 13, wherein the control logic determines the respective size requirements of the store operations and the load operations in the plurality of requests, wherein the cache memory performs a first cache memory access in response to a load operation request, the first cache memory access being limited in size to the size requirement for the load operation determined by the control logic, wherein the cache memory performs a second cache memory access in response to a store operation request, the second cache memory access being limited in size to the size requirement for the store operation determined by the control logic.

17. The IHS of claim 13, wherein the cache memory is an L2 cache memory.

18. The IHS of claim 13, wherein the processor element is a processor core that includes an L1 cache memory.