Network on chip with caching restrictions for pages of computer memory
First Claim
1. A network on chip (‘
- NOC’
) comprising;
integrated processor (‘
IP’
) blocks, routers, memory communications controllers, and network interface controllers, each IP block adapted to a router through a memory communications controller and a network interface controller, each memory communications controller controlling communications between an IP block and memory, each network interface controller controlling inter-IP block communications through routers;
a multiplicity of computer processors within the IP blocks, each computer processor implementing a plurality of hardware threads of execution; and
computer memory, the computer memory organized in pages and operatively coupled to one or more of the computer processors, the computer memory including a set associative cache, the cache comprising cache ways organized in sets, the cache being shared among the hardware threads of execution, each page of computer memory restricted for caching by one replacement vector of a class of replacement vectors to particular ways of the cache, each page of memory further restricted for caching by one or more bits of a replacement vector classification to particular sets of ways of the cache, each page of memory further restricted for caching by one or more bits of a replacement vector classification replacing bits in a cache index for a cache line of a memory page, the replaced bits added to a corresponding cache line tag to preserve the original address of the cache line.
1 Assignment
0 Petitions
Accused Products
Abstract
A network on chip (‘NOC’) that includes integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controllers, each IP block adapted to a router through a memory communications controller and a network interface controller, a multiplicity of computer processors, each computer processor implementing a plurality of hardware threads of execution; and computer memory, the computer memory organized in pages and operatively coupled to one or more of the computer processors, the computer memory including a set associative cache, the cache comprising cache ways organized in sets, the cache being shared among the hardware threads of execution, each page of computer memory restricted for caching by one replacement vector of a class of replacement vectors to particular ways of the cache, each page of memory further restricted for caching by one or more bits of a replacement vector classification to particular sets of ways of the cache.
131 Citations
18 Claims
-
1. A network on chip (‘
- NOC’
) comprising;integrated processor (‘
IP’
) blocks, routers, memory communications controllers, and network interface controllers, each IP block adapted to a router through a memory communications controller and a network interface controller, each memory communications controller controlling communications between an IP block and memory, each network interface controller controlling inter-IP block communications through routers;a multiplicity of computer processors within the IP blocks, each computer processor implementing a plurality of hardware threads of execution; and computer memory, the computer memory organized in pages and operatively coupled to one or more of the computer processors, the computer memory including a set associative cache, the cache comprising cache ways organized in sets, the cache being shared among the hardware threads of execution, each page of computer memory restricted for caching by one replacement vector of a class of replacement vectors to particular ways of the cache, each page of memory further restricted for caching by one or more bits of a replacement vector classification to particular sets of ways of the cache, each page of memory further restricted for caching by one or more bits of a replacement vector classification replacing bits in a cache index for a cache line of a memory page, the replaced bits added to a corresponding cache line tag to preserve the original address of the cache line. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
- NOC’
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10. A method of data processing with a network on chip (‘
- NOC’
), the NOC comprising;integrated processor (‘
IP’
) blocks, routers, memory communications controllers, and network interface controllers, each IP block adapted to a router through a memory communications controller and a network interface controller;a multiplicity of computer processors within the IP blocks, each computer processor implementing a plurality of hardware threads of execution; and computer memory, the computer memory organized in pages and operatively coupled to one or more of the computer processors, the computer memory including a set associative cache, the cache comprising cache ways organized in sets, the cache being shared among the hardware threads of execution; the method comprising; controlling by each memory communications controller communications between an IP block and memory, restricting each page of computer memory for caching by one replacement vector of a class of replacement vectors to particular ways of the cache; restricting each page of memory for caching by one or more bits of a replacement vector classification to particular sets of ways of the cache wherein restricting each page of memory for caching by one or more bits of a replacement vector classification to particular sets of ways of the cache further comprises; replacing, with one or more bits of a replacement vector classification one or more bits in a cache index for a cache line of a memory page; and preserving an original value of the cache index for the cache line by adding the one or more replaced bits to a corresponding cache line tag; and controlling by each network interface controller inter-IP block communications through routers. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18)
- NOC’
Specification