Mechanism for remapping post virtual machine memory pages

• US 8,195,914 B2
• Filed: 02/03/2011
• Issued: 06/05/2012
• Est. Priority Date: 12/27/2002
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Hall, Clifford D., Campbell, Randolph L.
• Primary Examiner(s): TSAI, SHENG JEN
• Application Number:
  US13/020,124
• Publication Number:
  US 20110131363A1
• Time in Patent Office: 488 Days
• Field of Search: 711/6, 711/207, 711/205, 711/E12.016, 711/E12.061
• US Class Current: 711/205
• CPC Class Codes: G06F 12/1036 for multiple virtual address spaces, e.g. segmentation G06F12/1045 takes precedence

Abstract

According to one embodiment, a computer system is disclosed. The computer system includes a processor, a chipset coupled to the processor and a memory coupled to the chipset. The chipset translates partitioned virtual machine memory addresses received from the processor to page level addresses.

Claims

1. A processor comprising:

partitioning logic to partition a memory by dividing the memory into a plurality of contiguous regions and allocating each one of the plurality of contiguous regions to each one of a plurality of virtual machines, the memory to store a plurality of page tables and a plurality of remap tables;

a first translation lookaside buffer to cache page table entries from the plurality of page tables; and

a memory controller including a second translation lookaside buffer to cache remap table entries from the plurality of remap tables, the second translation lookaside buffer and the plurality of remap tables to circumvent the partitioning by remapping memory addresses from the processor and an input/output device at page level granularity, where page size is less than region size.

2. The processor of claim 1 wherein the second translation lookaside buffer and the plurality of remap tables are to circumvent the partitioning by translating partitioned memory addresses to physical memory addresses.

3. The processor of claim 2 wherein the second translation lookaside buffer comprises:

an input that receives a partitioned memory address;

a remap directory coupled to the input;

a remap table coupled to the directory and the input; and

an output, coupled to the remap table, that transmits a physical memory address.

4. The processor of claim 2 further comprising:

an offset register coupled to the input/output device and the second translation lookaside buffer.

5. The processor of claim 4 wherein the second translation lookaside buffer controls the input/output device'"'"'s permission to access the memory.