System for dynamically allocating processing time to multiple threads

• US 8,195,922 B2
• Filed: 03/18/2005
• Issued: 06/05/2012
• Est. Priority Date: 03/18/2005
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell World Trade Limited (Marvell Technology Group Limited)
• Inventors: Chen, Hong-Yi, Sutardja, Sehat
• Primary Examiner(s): Faherty, Corey S
• Application Number:
  US11/084,364
• Publication Number:
  US 20060212687A1
• Time in Patent Office: 2,636 Days
• Field of Search: 712/228
• US Class Current: 712/205
• CPC Class Codes: G06F 9/3012 Organisation of register space, e.g. banked or distributed register file
• CPC Class Codes: G06F 9/30123 according to context, e.g. thread buffers
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3861 Recovery, e.g. branch miss-prediction, exception handling error detection or correction G06F11/00
• CPC Class Codes: G06F 9/3867 using instruction pipelines

Abstract

A pipeline processor architecture, processor, and methods are provided. In one implementation, a processor is provided that includes an instruction fetch unit operable to fetch instructions associated with a plurality of processor threads, a decoder responsive to the instruction fetch unit, issue logic responsive to the decoder, and a register file including a plurality of banks corresponding to the plurality of processor threads. Each bank is operable to store data associated with a corresponding processor thread. The processor can include a set of registers corresponding to each of a plurality of processor threads. Each register within a set is located either before or after a pipeline stage of the processor.

Claims

1. A processor, comprising:

a pipeline comprising multiple pipeline stages including an instruction fetch unit operable to fetch instructions associated with a plurality of processor threads, including a first processor thread and a second processor thread;

a set of registers corresponding to each of the plurality of processor threads, including the first processor thread and the second processor thread, the registers being located before and after each pipeline stage in the multiple pipeline stages of the pipeline of the processor;

wherein each pipeline stage includes a first selector in communication with input registers for that pipeline stage, and a second selector in communication with output registers for that pipeline stage, the input registers and the output registers being from the set of registers; and

a programmable controller operable to perform a context switch among the plurality of processor threads, including storing a state of a currently executing processor thread in a corresponding set of registers and loading a state of another processor thread from a corresponding set of registers to allow for processing of the another processor thread, by controlling switching of the first and second selectors such that data associated with the first processor thread pass through the corresponding first set of registers, and the multiple pipeline stages, during a time that the first processor thread is being processed, and data associated with the second processor thread pass through the corresponding second set of registers, and the multiple pipeline stages, during a time that the second processor thread is being processed, wherein the controller includes a plurality of hardware thread allocation counters corresponding to the plurality of processor threads to effect the context switch by the programmable controller within the processor, each thread allocation counter containing a first value representing a respective processor time allocation that controls a period of processor time that is to be dedicated to a respective processor thread, wherein the respective processor time allocation is fixed for and determined prior to the period of processor time, wherein the respective processor thread fully and exclusively uses the respective processor time allocation,

wherein the programmable controller is configured to dynamically change subsequent processor time allocations to the plurality of processor threads by changing one or more of the first values of the thread allocation counters to one or more second values based on a received input, the received input defining one or more portions of processor time to be allocated to each of the plurality of processor threads.

2. The processor of claim 1, wherein the first selector includes a multiplexer and the second selector includes a de-multiplexer.

3. The processor of claim 1, wherein the multiple pipeline stages further include one of decode logic, issue logic, execution unit, read logic, or write logic.

4. The processor of claim 1, wherein the controller controls switching of the first and second selectors based on input defining processor time to be allocated to each of the first processor thread and the second processor thread.

5. The processor of claim 4, wherein the controller is operable to control switching of the first and second selectors dynamically during execution of a program.

6. The processor of claim 1, further comprising:

a first interrupt handling routine to handle an interrupt request associated with the first processor thread; and

a second interrupt handling routine to handle an interrupt request associated with the second processor thread.

7. The processor of claim 6, wherein the first interrupt handling routine and the second interrupt handling routine have separate entry points.

8. The processor of claim 1, further comprising:

a first exception handling routine to handle an exception request associated with the first processor thread; and

a second exception handling routine to handle an exception request associated with the second processor thread.

9. The processor of claim 1, further comprising a single exception handling routine or a single interrupt handling routine to respectively handle substantially all exception requests or substantially all interrupt requests associated with both the first processor thread and the second processor thread.

34. The processor of claim 1, wherein the first value controls how many instructions are to be fetched at a time for the respective processor thread by the instruction fetch unit.

10. A processor, comprising:

a pipeline comprising multiple pipeline stages;

a set of registers corresponding to each of a plurality of processor threads, the registers within a set being located before and after each of the multiple pipeline stages of the processor;

a programmable controller operable to perform a context switch among the plurality of processor threads, including storing a state of a currently executing processor thread in a corresponding set of registers, and loading a state of another processor thread from a corresponding set of registers to allow for processing of the another processor thread, wherein the controller includes a plurality of thread allocation counters corresponding to the plurality of processor threads to effect the context switch by the programmable controller within the processor, each thread allocation counter containing a value representing a respective processor time allocation that controls a period of processor time that is to be dedicated to a respective processor thread, wherein the respective processor time allocation is fixed for and determined prior to the period of processor time, wherein the respective processor thread fully and exclusively uses the respective processor time allocation; and

circuitry configured to cause, based on an exception, a jump to one of a plurality of exception handling routines corresponding to the plurality of processor threads, wherein each of the plurality of exception handling routines handles an exception request associated with a corresponding processor thread.

11. The processor of claim 10, wherein the programmable controller is operable to perform the context switch at an end of an instruction cycle.

12. The processor of claim 10, further comprising a register file including a plurality of banks corresponding to each of the plurality of processor threads, each bank operable to store data associated with a corresponding processor thread.

13. The processor of claim 10, further comprising a plurality of program counters, each program counter operable to indicate an execution status of a corresponding processor thread.

14. The processor of claim 10, further comprising a plurality of interrupt handling routines corresponding to the plurality of processor threads, wherein each interrupt handling routine handles an interrupt request associated with a corresponding processor thread.

15. The processor of claim 14, wherein each of the plurality of interrupt handling routines have separate entry points.

16. A method comprising:

providing a first processor thread for instruction execution;

providing a second processor thread for instruction execution;

processing, on a processor, the first processor thread;

performing, on the processor, a context switch from the first processor thread to the second processor thread, wherein the performing comprises (a) storing a state of the first processor thread in a first set of registers corresponding to the first processor thread, the first set of registers comprising first registers located before and after each pipeline stage in multiple pipeline stages of a pipeline of the processor; and

(b) loading a state of the second processor thread from a second set of registers corresponding to the second processor thread, the second set of registers comprising second registers located before and after each pipeline stage in the multiple pipeline stages of the pipeline of the processor, wherein the performing comprises performing the context switch in accordance with signals from a programmable controller including at least first and second thread allocation counters corresponding to the first and second processor threads to effect the context switch by the programmable controller within the processor, each thread allocation counter containing a value representing how much processor time is to be allocated for a respective processor thread, wherein the programmable controller is operable to dynamically change processor time allocations to the first processor thread and the second processor thread;

using, on the processor, the first thread allocation counter to determine a weighting that corresponds to a first processor time allocation that controls a first period of processor time that is to be allocated to the first processor thread, wherein the first processor time allocation is fixed for and determined prior to the first period of processor time, wherein the first processor thread fully and exclusively uses the first processor time allocation; and

using, on the processor, the second thread allocation counter to determine a weighting that corresponds to a second processor time allocation that controls a second period of processor time that is to be allocated to the second processor thread, wherein the second processor time allocation is fixed for and determined prior to the second period of processor time, wherein the second processor thread fully and exclusively uses the second processor time allocation.

17. The method of claim 16, wherein storing a state of a given processor thread within a corresponding set of registers includes storing data corresponding to a pipeline stage of a processor.

18. The method of claim 16, further comprising:

receiving input changing a processor time allocation; and

performing a context switch among the first and second processor threads based on the changed processor time allocation.

19. The method of claim 16, wherein performing a context switch includes performing a context switch dynamically during execution of a program.

20. The method of claim 16, further comprising:

using a first interrupt handling routine to handle an interrupt request associated with the first processor thread; and

using a second interrupt handling routine to handle an interrupt request associated with the second processor thread.

21. The method of claim 20, wherein the first interrupt handling routine and the second interrupt handling routine have separate entry points.

22. The method of claim 16, further comprising:

using a first exception handling routine to handle an exception request associated with the first processor thread; and

using a second exception handling routine to handle an exception request associated with the second processor thread.

23. The method of claim 16, further comprising using a single exception handling routine or a single interrupt handling routine to respectively handle substantially all exception requests and substantially all interrupt requests associated with the first processor thread and the second processor thread.

24. A processor comprising:

a pipeline comprising multiple pipeline stages including (a) an instruction fetch unit operable to fetch instructions associated with a plurality of processor threads, (b) a decoder responsive to the instruction fetch unit, (c) issue logic responsive to the decoder, and (d) an execution unit in communication with the issue logic;

a set of registers corresponding to each of the plurality of processor threads, including the first processor thread and the second processor thread, the registers being located before and after each pipeline stage in the multiple pipeline stages of the pipeline of the processor;

a register file including a plurality of banks corresponding to the plurality of processor threads, each bank operable to only store data associated with a corresponding processor thread, wherein the execution unit is communicatively coupled with each of the banks; and

a programmable controller in communication with the instruction fetch unit, the controller operable to determine a processor thread from which a next instruction will be fetched by the instruction fetch unit, wherein the controller includes a plurality of thread allocation counters corresponding to the plurality of processor threads to effect the context switch by the programmable controller within the processor, each thread allocation counter containing a value representing a respective processor time allocation that controls a period of processor time that is to be dedicated to a respective processor thread by the instruction fetch unit, wherein the respective processor time allocation is fixed for and determined prior to the period of processor time, and wherein the respective processor thread fully and exclusively uses the respective processor time allocation.

25. The processor of claim 24, wherein the data includes operands or results of executed instructions associated with a given processor thread.

26. The processor of claim 24, wherein the controller is operable to perform a context switch among the plurality of processor threads, including storing a state of a currently executing processor thread in a corresponding set of registers, and loading a state of another processor thread from a corresponding set of registers to allow for processing of the another processor thread.

27. The processor of claim 24, wherein the controller is operable to perform a context switch including switching a selector that is in communication with the instruction fetch unit.

28. The processor of claim 27, wherein the selector includes a multiplexer or a de-multiplexer.

29. The processor of claim 27, wherein the controller is operable to control switching of the selector dynamically during execution of a program.

30. The processor of claim 27, wherein the controller is operable to control switching of the selector statically based on a pre-determined processor time allocation for each of the plurality of processor threads.

31. The processor of claim 24, wherein each of the plurality of processor threads has an associated exception handling routine for handling exceptions that is separate and independent from exception handling routines associated with other processor threads.

32. The processor of claim 24, wherein each of the plurality of processor threads has an associated interrupt handling routine for handling interrupts that is separate and independent from interrupt handling routines associated with other processor threads.

33. The processor of claim 32, wherein each of the plurality of interrupt handling routines has a separate entry point.