Apparatus, system, and method for detecting and replacing failed data storage

• US 8,195,978 B2
• Filed: 05/18/2009
• Issued: 06/05/2012
• Est. Priority Date: 05/16/2008
• Status: Expired due to Fees

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Fusion-IO Incorporated (Western Digital Corporation)
• Inventors: Flynn, David, Thatcher, Jonathan, Aune, Joshua, Fillingim, Jeremy, Inskeep, Bill, Strasser, John, Vigor, Kevin
• Primary Examiner(s): BONZO, BRYCE P
• Application Number:
  US12/467,914
• Publication Number:
  US 20090287956A1
• Time in Patent Office: 1,114 Days
• Field of Search: 714/6
• US Class Current: 714/6.1
• CPC Class Codes: G06F 11/1008 in individual solid state devices G06F11/1004 takes precedence
• CPC Class Codes: G06F 11/108 Parity data distribution in semiconductor storages, e.g. in SSD
• CPC Class Codes: G06F 2211/109 Sector level checksum or ECC, i.e. sector or stripe level checksum or ECC in addition to the RAID parity calculation
• CPC Class Codes: G11C 29/765 in solid state disks

Abstract

An apparatus, system, and method are disclosed for detecting and replacing failed data storage. A read module reads data from an array of memory devices. The array includes two or more memory devices and one or more extra memory devices storing parity information from the memory devices. An ECC module determines, using an error correcting code (“ECC”), if one or more errors exist in tested data and if the errors are correctable using the ECC. The tested data includes data read by the read module. An isolation module selects a memory device in response to the ECC module determining that errors exists in the data read by the read module and that the errors are uncorrectable using the ECC. The isolation module also replaces data read from the selected memory device with replacement data and available data wherein the tested data includes the available data combined with the replacement data.

Claims

1. An apparatus to detect and replace failed data storage, the apparatus comprising:

a read module that reads an error correcting code (ECC) chunk stored across a plurality of memory devices of an array of memory devices, the ECC chunk comprising both data and an error correcting code derived from the data and wherein at least one of the memory devices of the array stores parity data derived from data stored on each memory device of the plurality of memory devices storing the ECC chunk;

an ECC module that determines that the ECC chunk has more errors than are correctable using the error correcting code for the ECC chunk; and

an isolation module that tests individual memory devices of the plurality of memory devices to locate a failed memory device by;

substituting, within the data of the ECC chunk, replacement data for data of a first one of the memory devices to form a first substitute ECC chunk, the replacement data derived from the parity data;

substituting, within the data of the ECC chunk, replacement data for data of a second one of the memory devices to form a second substitute ECC chunk in response to the ECC module determining that the first substitute ECC chunk has more errors than are correctable using the error correcting code for the ECC chunk; and

determining that the second one of the memory devices is the failed memory device in response to the ECC module determining that errors in the second substitute ECC chunk are correctable using the error correcting code for the ECC chunk.

2. The apparatus of claim 1, further comprising a retirement module that retires one or more storage regions on the second one of the memory devices based on a retirement policy, the one or more storage regions comprising one or more errors.

3. The apparatus of claim 1, further comprising a memory device reconfiguration module that identifies the second one of the memory devices and generates data to replace data read from the second one of the memory devices for future operations.

4. The apparatus of claim 1, further comprising a logging module that, in response to the ECC module determining that errors in the second substitute ECC chunk are correctable using the ECC, one or more of

logs an identity of the second one of the memory devices;

and

logs memory location data specifying one or more storage regions comprising one or more errors, the regions comprising at least a portion of the second one of the memory devices.

5. The apparatus of claim 4, wherein the logging module logs the identity of the second one of the memory devices without logging memory location data comprising a storage region with one or more errors.

6. The apparatus of claim 5, further comprising a storage region testing module that identifies one or more storage regions comprising errors within the second one of the memory devices, and wherein the logging module further logs memory location data comprising the one or more storage regions identified by the storage region testing module.

7. The apparatus of claim 6, wherein the storage region testing module identifies storage regions with one or more errors with subsequent reads by the read module and using the ECC module and the isolation module to determine storage regions with uncorrectable errors that are correctable using the parity data.

8. The apparatus of claim 4, wherein the logging module logs one or more storage regions comprising one or more errors and further logs memory location data specifying one or more additional storage regions comprising one or more errors in the second one of the memory devices, in response to subsequent reads by the read module and using the ECC module and the isolation module to determine storage regions with uncorrectable errors that are correctable using the replacement data.

9. The apparatus of claim 8, wherein a subsequent read comprises one of a read initiated by a storage region testing module and a read from a read request.

10. The apparatus of claim 4, further comprising an area reconfiguration module that replaces data in the one or more storage regions in the second one of the selected memory devices with replacement data from one or more extra memory devices for future operations such that data outside the one or more storage regions in the second one of the selected memory devices is not replaced.

11. The apparatus of claim 10, wherein the area reconfiguration module replaces data from the one or more storage regions of the second one of the memory devices with replacement data from one or more extra memory devices and replaces data from one or more additional storage regions on the second one of the memory devices or a different memory device of the array with replacement data from the same one or more extra memory devices, each of the one or more additional storage regions comprising one or more errors, wherein the one or more storage regions and the one or more additional storage regions do not share a common logical page.

12. The apparatus of claim 10, wherein the area reconfiguration module replaces data from the one or more storage regions with replacement data from one or more extra memory devices and replaces one or more additional storage regions with replacement data from one or more different extra memory devices, each of the one or more additional storage regions comprising one or more errors, wherein the one or more storage regions and the one or more additional storage regions share a common logical page.

13. The apparatus of claim 4, wherein a storage region comprises one or more of one or more ECC chunks, one or more physical pages, one or more logical pages, one or more physical erase blocks, one or more logical erase blocks, a chip, a portion of a chip, a portion of one or more dies, and one or more dies.

14. The apparatus of claim 4, further comprising an analysis module that analyzes the log to determine one or more of an area in the second one of the memory devices with data errors and an error type.

15. The apparatus of claim 1, further comprising an error storage recovery module that erases an erase block of the second one of the memory devices, the erase block comprising a portion of the ECC chunk, to prepare the erase block for future data storage in response to the ECC module determining that errors in the second substitute ECC chunk are correctable using the error correcting code.

16. The apparatus of claim 15, wherein a retirement module retires the erase block and uses replacement data from one or more extra memory devices in place of data from the erase block in response to

the error storage recovery module erasing the erase block,

subsequently writing additional data to the erase block,

a subsequent read of the additional data by the read module, and

using the ECC module and the isolation module to determine that the erase block comprises uncorrectable errors that are correctable using additional replacement data associated with the additional data.

17. The apparatus of claim 1, wherein the read module reads the ECC chunk from at least a portion of a logical page, the logical page spanning the array of memory devices, the array of memory devices comprising an array of N+P number of storage elements, the array of storage elements comprising N number of the storage elements each storing a portion of an ECC chunk and P number of the storage elements storing parity data, the ECC chunk comprising stored data and ECC generated from the stored data wherein the ECC spans the stored data, the P number of storage elements storing parity data generated from the ECC chunk stored in the N number of the storage elements.

18. The apparatus of claim 1, further comprising a correct data module that returns corrected data in response to the ECC module determining that errors in the second substitute ECC chunk are correctable using the ECC.

19. The apparatus of claim 1, further comprising a reporting module that reports the failed memory device in response to the ECC module determining that errors in the second substitute ECC chunk are correctable using the ECC.

20. The apparatus of claim 1, wherein each memory device comprises non-volatile solid-state storage.

21. A system to detect and replace failed data storage, the system comprising:

an array of memory devices, the array comprising two or more memory devices and one or more extra memory devices, the extra memory devices storing parity information from data stored on each memory device of the two or more memory devices; and

a storage controller that;

reads an error correcting code (ECC) chunk stored across the array of memory devices, the ECC chunk comprising both data and an error correcting code derived from the data;

determines that the ECC chunk has more errors than are correctable using the error correcting code for the ECC chunk;

tests individual memory devices of the plurality of memory devices to locate a failed memory device by iteratively substituting, within the data of the ECC chunk, replacement data derived from the parity information for individual memory devices of the array to form substitute ECC chunks until one of the substitute ECC chunks is correctable using the error correcting code for the ECC chunk; and

determines that the memory device associated with the one substitute ECC chunk is the failed memory device.

22. A data storage method comprising:

reading an error correcting code (ECC) chunk stored across a plurality of memory devices of an array of memory devices, the ECC chunk comprising both data and an error correcting code derived from the data and wherein at least one of the memory devices of the array stores parity data derived from data stored on each memory device of the plurality of memory devices storing the ECC chunk;

determining that the ECC chunk has more errors than are correctable using the error correcting code for the ECC chunk;

testing individual memory devices of the plurality of memory devices to locate a failed memory device by iteratively substituting, within the data of the ECC chunk, replacement data derived from the parity data for individual memory devices of the plurality to form substitute ECC chunks until one of the substitute ECC chunks is correctable using the error correcting code for the ECC chunk; and

determining that the memory device associated with the one substitute ECC chunk is the failed memory device.