Methods and apparatus for interleaving in a block-coherent communication system

• US 8,196,000 B2
• Filed: 06/11/2007
• Issued: 06/05/2012
• Est. Priority Date: 04/02/2003
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Jin, Hui, Richardson, Tom, Novichkov, Vladimir
• Primary Examiner(s): Abraham, Esaw T
• Application Number:
  US11/761,359
• Publication Number:
  US 20070234175A1
• Time in Patent Office: 1,821 Days
• Field of Search: 714/702, 714/752, 714/786
• US Class Current: 714/752
• CPC Class Codes: H03M 13/116 Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
• CPC Class Codes: H03M 13/2757 Interleaver with an interleaving rule not provided for in the subgroups H03M13/2703 - H03M13/2753
• CPC Class Codes: H03M 13/2957 Turbo codes and decoding
• CPC Class Codes: H03M 13/6331 Error control coding in combination with equalisation
• CPC Class Codes: H04L 1/0057 Block codes H04L1/0061, H04L1/0064 take precedence
• CPC Class Codes: H04L 1/0071 Use of interleaving interleaving per se H03M13/27
• CPC Class Codes: H04L 25/03318 Provision of soft decisions

Abstract

A method, apparatus, and machine readable medium for processing a plurality of Z-vectors. Each Z-vector includes Z elements, and each element includes K bits. The Z-vectors correspond to a binary codeword, portions of which have a relationship to a plurality of transmission units. The Z-vectors are stored in a set of D memory arrays. Each memory array includes Z rows of memory locations. Each memory location corresponds to a different array column, and each array column corresponds to a different Z-vector. Each Z-vector identifies one column. A series of sets of control information is generated. Each set includes a transmission unit identifier, a Z-vector identifier, and a row identifier. For at least one set, P times K divided by D bits is read from each column identified by the Z-vector that is identified by the Z-vector identifier included in the set.

Claims

1. A method of processing a plurality of Z-vectors, each Z-vector including Z elements, each element including K bits, where Z is a positive integer greater than 1 and K is a positive integer, the plurality of Z-vectors corresponding to a binary codeword, portions of said binary codeword having a direct mapping relationship to a plurality of transmission units, said plurality of Z-vectors being stored in a set of D memory arrays, where D is an integer greater than zero, each memory array including Z rows of memory locations, each memory location of a row corresponding to a different array column, each array column corresponding to a different one of said plurality of Z-vectors, each Z-vector identifying one column in each of said D memory arrays, the method comprising:

generating a series of sets of control information, each set of control information including;

i) a transmission unit identifier;

ii) a Z-vector identifier;

iii) a row identifier; and

for at least one generated set of control information;

reading P times K divided by D bits, where P is a positive integer, from each column identified by the Z-vector that is identified by the Z-vector identifier included in said at least one generated set of control information.

2. An apparatus for processing a plurality of Z-vectors, each Z-vector including Z elements, each element including K bits, where Z is a positive integer greater than 1 and K is a positive integer, the plurality of Z-vectors corresponding to a binary codeword, portions of said binary codeword having a direct mapping relationship to a plurality of transmission units, said apparatus comprising:

memory including a set of D memory arrays for storing said plurality of Z-vectors, where D is an integer greater than zero, each memory array including Z rows of memory locations, each memory location of a row corresponding to a different array column, each array column corresponding to a different one of said plurality of Z-vectors, each Z-vector identifying one column in each of said D memory arrays;

memory access control module for generating a series of sets of control information, each set of control information including;

i) a transmission unit identifier;

ii) a Z-vector identifier;

iii) a row identifier; and

means for reading P times K divided by D bits, from said memory, where P is a positive integer, from each column identified by the Z-vector identified by the Z-vector identifier included at least one generated set of control information.

3. A machine readable medium comprising machine executable instructions for controlling a computer device to process a plurality of Z-vectors, each Z-vector including Z elements, each element including K bits, where Z is a positive integer greater than 1 and K is a positive integer, the plurality of Z-vectors corresponding to a binary codeword, portions of said binary codeword having a direct mapping relationship to a plurality of transmission units, said machine executable instructions including instructions used to control the computer device to:

generate a series of sets of control information, each set of control information including;

i) a transmission unit identifier;

ii) a Z-vector identifier; and

iii) a row identifier; and

for at least one generated set of control information;

read P times K divided by D bits, where P is a positive integer, from each column identified by the Z-vector identified by the Z-vector identifier included in said at least one generated set of control information.