Cell-library-for-statistical-timing-analysis creating apparatus and statistical-timing analyzing apparatus

• US 8,196,077 B2
• Filed: 01/11/2010
• Issued: 06/05/2012
• Est. Priority Date: 03/17/2009
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Yoda, Tomoyuki
• Primary Examiner(s): Siek, Vuthe
• Application Number:
  US12/685,066
• Publication Number:
  US 20100242007A1
• Time in Patent Office: 876 Days
• Field of Search: 716/106, 716/108, 716/113, 716/134, 716/136
• US Class Current: 716/108
• CPC Class Codes: G06F 2111/08 Probabilistic or stochastic CAD
• CPC Class Codes: G06F 2119/12 Timing analysis or timing optimisation
• CPC Class Codes: G06F 30/3323 using formal methods, e.g. equivalence checking or property checking

Abstract

A cell-library-for-statistical-timing-analysis creating apparatus includes: a unit that groups cells into groups of cells each having the same topology; a unit that selects representative cells from the respective grouped cell group; a unit that sets one or more kinds of signal transition time information based on output signal transition time and input signal transition time; a unit that calculates, for each of the representative cells, an output load capacitance and input signal transition time for each of kinds of signal transition time information; a unit that executes circuit simulation using the output load capacitance and the input signal transition time and calculates a delay variation amount; a unit that calculates delay variation information based on a delay average and the delay variation amount; and a unit that outputs association for each of the representative cells between the signal transition time information and the delay variation information.

Claims

1. A cell-library-for-statistical-timing-analysis creating apparatus, comprising:

a group determining unit that groups cells as statistical timing analysis targets into groups of cells each having same topology;

a representative-cell selecting unit that selects representative cells from the respective grouped cell groups;

a signal-transition-time-information determining unit that sets one or more kinds of signal transition time information based on output signal transition time as transition time of an output signal from a cell and input signal transition time as transition time of an input signal to the cell;

an output-load-capacitance/input-signal-transition-time determining unit that calculates, based on the set signal transition time information and a cell library for static timing analysis, for each of the selected representative cells, an output load capacitance and input signal transition time for each of the set kinds of signal transition time information to be used for circuit simulation;

a circuit-simulation executing unit that executes the circuit simulation using the calculated output load capacitance and input signal transition time and calculates a delay variation amount;

a delay-variation-information calculating unit that calculates delay variation information based on a delay average and the delay variation amount calculated by the circuit simulation; and

a library output unit that outputs, as a cell library for statistical timing analysis, association for each of the representative cells between the signal transition time information and the delay variation information.

2. The cell-library-for-statistical-timing-analysis creating apparatus according to claim 1, wherein the cell library for static timing analysis is a table for associating the input signal transition and output load capacitance of the cells and the output signal transition time.

3. The cell-library-for-statistical-timing-analysis creating apparatus according to claim 2, wherein the output-load-capacitance/input-signal-transition-time determining unit calculates, based on the signal transition time information set by the signal-transition-time-information determining unit, input signal transition time used for the circuit simulation and output signal transition time corresponding to the input signal transition time and calculates an output load capacitance that satisfies a correspondence relation between the calculated input signal transition time to be used for the circuit simulation and the output signal transition time corresponding to the input signal transition time in the cell library for static timing analysis.

4. The cell-library-for-statistical-timing-analysis creating apparatus according to claim 3, wherein the output-load-capacitance/input-signal-transition-time determining unit binary-searches through the cell library for static timing analysis based on the calculated input signal transition time to be used for the circuit simulation and the output signal transition time corresponding to the input signal transition time to thereby calculates the output load capacitance.

5. The cell-library-for-statistical-timing-analysis creating apparatus according to claim 3, wherein the signal transition time information is a signal transition time ratio as a ratio of the input signal transition time and the output signal transition time.

6. The cell-library-for-statistical-timing-analysis creating apparatus according to claim 3, wherein the delay variation information is a delay variation ratio as a ratio of the delay variation amount and the delay average value.

7. The cell-library-for-statistical-timing-analysis creating apparatus according to claim 1, wherein the representative-cell selecting unit selects cells having smallest transistor sizes as the representative cells in the grouped respective cell groups.

8. A statistical-timing analyzing apparatus, comprising:

a net-delay analyzing unit that calculates, for each of nets forming a path, a delay average and a delay variation amount of a cell arranged in a pre-stage of the net; and

a path-delay analyzing unit that calculates a path delay of the path based on the delay average and the delay variation amount calculated for each of the nets, wherein

the net-delay analyzing unit includes;

a net selecting unit that selects a net forming the path;

a delay-average/output-signal-transition-time calculating unit that calculates a delay average and output signal transition time referring to a cell library for static timing analysis with input signal transition time to a cell arranged in a pre-stage of the selected net and an output load capacitance of the cell set as search keys;

a signal-transition-time-ratio calculating unit that divides the calculated output signal transition time by the input signal transition time to calculate a signal transition time ratio;

a delay-variation-ratio calculating unit that calculates a delay variation ratio referring to a cell library for statistical timing analysis with the calculated signal transition time ratio set as a search key; and

a delay-variation-amount calculating unit that multiplies the calculated delay average and the calculated delay variation ratio together to calculate a delay variation amount, wherein

the cell library for statistical timing analysis is created by a cell-library-for-statistical-timing-analysis creating apparatus including;

a group determining unit that groups cells as statistical timing analysis targets into groups of cells each having same topology;

a representative-cell selecting unit that selects representative cells from the respective grouped cell groups;

a signal-transition-time-information determining unit that sets one or more signal transition time ratios as ratios of the input signal transition time and the output signal transition time;

an output-load-capacitance/input-signal-transition-time determining unit that calculates, based on the signal transition time ratios set by the signal-transition-time-information determining unit and the cell library for static timing analysis, for each of the selected representative cells, an output load capacitance and input signal transition time for each of the set signal transition time ratios to be used for circuit simulation;

a circuit-simulation executing unit that executes the circuit simulation using the output load capacitance and the input signal transition time calculated by the output-load-capacitance/input-signal-transition-time determining unit and calculates a delay variation amount;

a delay-variation-information calculating unit that calculates a delay variation ratio as a ratio of the delay variation amount calculated by the circuit-simulation executing unit and the delay average; and

a library output unit that outputs, as the cell library for statistical timing analysis, association for each of the representative cells between the signal transition time ratio and the delay variation ratio calculated by the delay-variation-information calculating unit.

9. The statistical-timing analyzing apparatus according to claim 8, wherein the cell library for static timing analysis is a table for associating the input signal transition and output load capacitance of the cells and the output signal transition time.

10. The statistical-timing analyzing apparatus according to claim 9, wherein the output-load-capacitance/input-signal-transition-time determining unit calculates, based on the signal transition time ratios set by the signal-transition-time-information determining unit, input signal transition time used for the circuit simulation and output signal transition time corresponding to the input signal transition time and calculates an output load capacitance that satisfies a correspondence relation between the calculated input signal transition time to be used for the circuit simulation and the output signal transition time corresponding to the input signal transition time in the cell library for static timing analysis.

11. The statistical-timing analyzing apparatus according to claim 10, wherein the output-load-capacitance/input-signal-transition-time determining unit binary-searches through the cell library for static timing analysis based on the calculated input signal transition time to be used for the circuit simulation and the output signal transition time corresponding to the input signal transition time to thereby calculates the output load capacitance.

12. The statistical-timing analyzing apparatus according to claim 8, wherein

the path delay of the path calculated by the path-delay analyzing unit includes a path delay average as an average of delay times of the path and a path delay standard deviation as a standard deviation of the delay times, and

the path-delay analyzing unit integrates the calculated delay average of each of the nets forming the path to calculate the path delay average, squares the calculated delay variation amount for each of the nets forming the path, integrate the squared values and raises the integrated value to the 0.5th power to calculate the path delay standard deviation.

13. The statistical-timing analyzing apparatus according to claim 8, wherein the representative-cell selecting unit selects cells having smallest transistor sizes as the representative cells in the grouped respective cell groups.

14. A statistical-timing analyzing apparatus, comprising:

a cell-library-for-statistical-timing-analysis creating unit that creates a first cell library for statistical timing analysis, which outputs a delay variation amount with the input signal transition time and the output load capacitance set as search keys, using a second cell library for statistical timing analysis created by a cell-library-for-statistical-timing-analysis including;

a group determining unit that groups cells as statistical timing analysis targets into groups of cells each having same topology;

a representative-cell selecting unit that selects representative cells from the respective grouped cell groups;

a signal-transition-time-information determining unit that sets one or more signal transition time ratios as ratios of input signal transition time as transition time of an input signal to a cell and output signal transition time of an output signal from the cell;

an output-load-capacitance/input-signal-transition-time determining unit that calculates, based on the set signal transition time ratios and a cell library for static timing analysis, for each of the selected representative cells, an output load capacitance and input signal transition time for each of the set signal transition time ratios to be used for circuit simulation;

a circuit-simulation executing unit that executes the circuit simulation using the calculated output load capacitance and input signal transition time and calculates a delay variation amount;

a delay-variation-information calculating unit that calculates a delay variation ratio as a ratio of the delay variation amount calculated by the circuit simulation and the delay average; and

a library output unit that outputs, as the second cell library for statistical timing analysis, association for each of the representative cells between the signal transition time ratio and the delay variation ratio; and

a statistical-timing-analysis executing unit that executes statistical timing analysis based on the first cell library for statistical timing analysis, wherein

the cell-library-for-statistical-timing-analysis creating unit includes;

an input-signal-transition-time/output-load-capacitance setting unit that selects one input signal transition time and one output load capacitance out of a plurality of input signal transition times and a plurality of output load capacities, respectively;

a delay-average/output-signal-transition-time calculating unit that calculates a delay average and output signal transition time referring to the cell library for static timing analysis with the input signal transition time and the output load capacitance selected by the input-signal-transition-time/output-load-capacitance setting unit set as search keys;

a signal-transition-time-ratio calculating unit that divides the output signal transition time calculated by the delay-average/output-signal-transition-time calculating unit by the input signal transition time selected by the input-signal-transition-time/output-load-capacitance setting unit to calculate a signal transition time ratio;

a delay-variation-ratio calculating unit that calculates a delay variation ratio referring to the second cell library for statistical timing analysis with the signal transition time ratio calculated by the signal-transition-time-ratio calculating unit set as a search key; and

a delay-variation-amount calculating unit that multiplies the delay average calculated by the delay-average/output-signal-transition-time calculating unit and the delay variation ratio calculated by the delay-variation-ratio calculating unit together to calculate a delay variation amount.

15. The statistical-timing analyzing apparatus according to claim 14, wherein the cell library for static timing analysis is a table for associating the input signal transition and output load capacitance of the cells and the output signal transition time.

16. The statistical-timing analyzing apparatus according to claim 15, wherein the output-load-capacitance/input-signal-transition-time determining unit calculates, based on the signal transition time information set by the signal-transition-time-information determining unit, input signal transition time used for the circuit simulation and output signal transition time corresponding to the input signal transition time and calculates an output load capacitance that satisfies a correspondence relation between the calculated input signal transition time to be used for the circuit simulation and the output signal transition time corresponding to the input signal transition time in the cell library for static timing analysis.

17. The statistical-timing analyzing apparatus according to claim 16, wherein the output-load-capacitance/input-signal-transition-time determining unit binary-searches through the cell library for static timing analysis based on the calculated input signal transition time to be used for the circuit simulation and the output signal transition time corresponding to the input signal transition time to thereby calculates the output load capacitance.

18. The statistical-timing analyzing apparatus according to claim 14, wherein the representative-cell selecting unit selects cells having smallest transistor sizes as the representative cells in the grouped respective cell groups.