Security circuit for power up
First Claim
1. A circuit for securing against non-reset of a device associated with the circuit, the circuit comprising:
- a first register for holding a first multi-bit value and to produce a first multi-bit output value related to the first multi-bit value;
a second register for holding a second multi-bit value and to produce a second multi-bit output value related to the second multi-bit value;
an inverter coupled to receive as an input only one of the first and second multi-bit output values and invert the input to output an inverted multi-bit output value wherein each bit is the inverse of the input; and
a comparator arranged to compare the inverted and non-inverted multi-bit output values to produce a comparator output indicating a match or mismatch between the inverted and non-inverted output values,wherein the first and second registers are arranged such that they are subject to substantially the same operational conditions.
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Accused Products
Abstract
A circuit and method for securing against non-reset of a device associated with the circuit, the circuit comprising: a first register for holding a first multi-bit value and to produce a first multi-bit output value related to the first multi-bit value; a second register for holding a second multi-bit value and to produce a second multi-bit output value related to the second multi-bit value; an inverter means arranged to invert only one of the first and second output values; and a comparator arranged to compare the inverted and non-inverted output values to produce a comparator output, wherein the first and second registers are arranged such that they are subject to substantially the same operational conditions.
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Citations
15 Claims
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1. A circuit for securing against non-reset of a device associated with the circuit, the circuit comprising:
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a first register for holding a first multi-bit value and to produce a first multi-bit output value related to the first multi-bit value; a second register for holding a second multi-bit value and to produce a second multi-bit output value related to the second multi-bit value; an inverter coupled to receive as an input only one of the first and second multi-bit output values and invert the input to output an inverted multi-bit output value wherein each bit is the inverse of the input; and a comparator arranged to compare the inverted and non-inverted multi-bit output values to produce a comparator output indicating a match or mismatch between the inverted and non-inverted output values, wherein the first and second registers are arranged such that they are subject to substantially the same operational conditions. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A method of resetting a circuit associated with a device, comprising the steps of:
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loading each of a first and second register which are subject to substantially the same operational conditions with the same multi-bit value; producing a first multi-bit output value related to the multi-bit value from the first register; producing a second multi-bit output value related to the multi-bit value from the second register; receiving as an input only one of the first and second multi-bit output values; inverting the input to output an inverted multi-bit output value wherein each bit is the inverse of the input; and comparing the inverted and non-inverted output values to provide an indication that the device is in secure mode. - View Dependent Claims (8, 9)
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10. A method of indicating a secure state of a circuit associated with a device without resetting on power-up of the circuit, comprising the steps of:
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allowing a first register to settle to a first multi-bit value and produce a first multi-bit output value related to the first multi-bit value; allowing a second register to settle to a second multi-bit value and produce a second multi-bit output value related to the second multi-bit value; receiving as an input only one of the first and second multi-bit output values; inverting the input to output an inverted multi-bit output value wherein each bit is the inverse of the input; and comparing the inverted and non-inverted output values to produce a comparator output indicating a match or mismatch between the inverted and non-inverted output values, wherein the first and second registers are arranged such that they are subject to substantially the same operational conditions and thereby tend to settle to the same multi-bit values. - View Dependent Claims (11, 12)
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13. A device comprising a circuit for securing against non-reset of a device associated with the circuit, the circuit comprising:
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a first register for holding a first multi-bit value and to produce a first multi-bit output value related to the first multi-bit value; a second register for holding a second multi-bit value and to produce a second multi-bit output value related to the second multi-bit value; an inverter coupled to receive as an input only one of the first and second multi-bit output values and invert the input to output an inverted multi-bit output value wherein each bit is the inverse of the input; and a comparator arranged to compare the inverted and non-inverted multi-bit output values to produce a comparator output indicating a match or mismatch between the inverted and non-inverted output values, wherein the first and second registers are arranged such that they are subject to substantially the same operational conditions. - View Dependent Claims (14, 15)
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Specification