Security circuit for power up

• US 8,196,215 B2
• Filed: 12/05/2008
• Issued: 06/05/2012
• Est. Priority Date: 12/14/2007
• Status: Active Grant

• Current Assignee: Icera Inc. (NVIDIA Corporation)
• Original Assignee: Icera Inc. (NVIDIA Corporation)
• Inventors: Dewar, Kevin
• Primary Examiner(s): JUNG, DAVID YIUK
• Application Number:
  US12/328,952
• Publication Number:
  US 20090158445A1
• Time in Patent Office: 1,278 Days
• Field of Search: 726/34
• US Class Current: 726/34
• CPC Class Codes: G06F 1/24 Resetting means
• CPC Class Codes: G06F 2221/2105 Dual mode as a secondary aspect
• CPC Class Codes: H03K 17/22 Modifications for ensuring a predetermined initial state when the supply voltage has been applied bi-stable generators H03K3/12

Abstract

A circuit and method for securing against non-reset of a device associated with the circuit, the circuit comprising: a first register for holding a first multi-bit value and to produce a first multi-bit output value related to the first multi-bit value; a second register for holding a second multi-bit value and to produce a second multi-bit output value related to the second multi-bit value; an inverter means arranged to invert only one of the first and second output values; and a comparator arranged to compare the inverted and non-inverted output values to produce a comparator output, wherein the first and second registers are arranged such that they are subject to substantially the same operational conditions.

Claims

1. A circuit for securing against non-reset of a device associated with the circuit, the circuit comprising:

a first register for holding a first multi-bit value and to produce a first multi-bit output value related to the first multi-bit value;

a second register for holding a second multi-bit value and to produce a second multi-bit output value related to the second multi-bit value;

an inverter coupled to receive as an input only one of the first and second multi-bit output values and invert the input to output an inverted multi-bit output value wherein each bit is the inverse of the input; and

a comparator arranged to compare the inverted and non-inverted multi-bit output values to produce a comparator output indicating a match or mismatch between the inverted and non-inverted output values,

wherein the first and second registers are arranged such that they are subject to substantially the same operational conditions.

2. A circuit according to claim 1, wherein if the comparator output indicates that the first and second multi-bit values are the same, the device is in a secure mode and if the comparator output indicates that the first and second multi-bit values are not the same, the device is in a non-secure mode.

3. A circuit according to claim 1, wherein the first and second registers are located in close proximity to one another so as to be subject to substantially the same operational conditions.

4. A circuit according to claim 1, wherein the comparator is arranged to compare the respective multi-bit inverted and non-inverted output values substantially in parallel.

5. A circuit according to claim 1, wherein the first register is arranged to be loaded with the first multi-bit value and the second register is arranged to be loaded with the second multi-bit value, the first and second multi-bit values being identical.

6. A circuit according to claim 1, wherein one of the first and second multi-bit values is a function of a user input to the device and the other of the first and second multi-bit values is a stored value.

7. A method of resetting a circuit associated with a device, comprising the steps of:

loading each of a first and second register which are subject to substantially the same operational conditions with the same multi-bit value;

producing a first multi-bit output value related to the multi-bit value from the first register;

producing a second multi-bit output value related to the multi-bit value from the second register;

receiving as an input only one of the first and second multi-bit output values;

inverting the input to output an inverted multi-bit output value wherein each bit is the inverse of the input; and

comparing the inverted and non-inverted output values to provide an indication that the device is in secure mode.

8. A method according to claim 7, wherein the first and second registers are located in close proximity to one another so as to be subject to substantially the same operational conditions.

9. A method according to claim 7, wherein the step of comparing all the respective inverted and non-inverted multi-bit output values is carried out substantially in parallel.

10. A method of indicating a secure state of a circuit associated with a device without resetting on power-up of the circuit, comprising the steps of:

allowing a first register to settle to a first multi-bit value and produce a first multi-bit output value related to the first multi-bit value;

allowing a second register to settle to a second multi-bit value and produce a second multi-bit output value related to the second multi-bit value;

receiving as an input only one of the first and second multi-bit output values;

inverting the input to output an inverted multi-bit output value wherein each bit is the inverse of the input; and

comparing the inverted and non-inverted output values to produce a comparator output indicating a match or mismatch between the inverted and non-inverted output values,

wherein the first and second registers are arranged such that they are subject to substantially the same operational conditions and thereby tend to settle to the same multi-bit values.

11. A method according to claim 10, wherein the first and second registers are located in close proximity to one another so as to be subject to substantially the same operational conditions.

12. A method according to claim 10, wherein the step of comparing all the respective inverted and non-inverted multi-bit output values is carried out substantially in parallel.

13. A device comprising a circuit for securing against non-reset of a device associated with the circuit, the circuit comprising:

a first register for holding a first multi-bit value and to produce a first multi-bit output value related to the first multi-bit value;

a second register for holding a second multi-bit value and to produce a second multi-bit output value related to the second multi-bit value;

an inverter coupled to receive as an input only one of the first and second multi-bit output values and invert the input to output an inverted multi-bit output value wherein each bit is the inverse of the input; and

a comparator arranged to compare the inverted and non-inverted multi-bit output values to produce a comparator output indicating a match or mismatch between the inverted and non-inverted output values,

wherein the first and second registers are arranged such that they are subject to substantially the same operational conditions.

14. A device according to claim 13, comprising a memory for storing the first and second multi-bit values to be loaded into the first and second registers.

15. A device according to claim 13, wherein the first and second registers are located in close proximity to one another so as to be subject to substantially the same operational conditions.