Schottky diode switch and memory units containing the same

• US 8,198,181 B1
• Filed: 02/20/2012
• Issued: 06/12/2012
• Est. Priority Date: 07/13/2009
• Status: Expired due to Fees

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Inventors: Kim, Young Pil, Amin, Nurul, Setiadi, Dadi, Vaithyanathan, Venugopalan, Tian, Wei, Jin, Insik
• Primary Examiner(s): Malsawma, Lex
• Application Number:
  US13/400,364
• Publication Number:
  US 20120149183A1
• Time in Patent Office: 113 Days
• Field of Search: 438/514, 257/E21.211
• US Class Current: 438/514
• CPC Class Codes: G11C 11/161 details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 13/0002 using resistive RAM [RRAM] elements
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/0814 Diodes only
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/20 including, apart from doping materials or other impurities, only AIIIBV compounds
• CPC Class Codes: H01L 29/66143 Schottky diodes
• CPC Class Codes: H01L 29/66212 Schottky diodes
• CPC Class Codes: H01L 29/872 Schottky diodes
• CPC Class Codes: H10B 53/30 characterised by the memory core region
• CPC Class Codes: H10B 61/10 comprising components having two electrodes, e.g. diodes or MIM elements
• CPC Class Codes: H10B 63/20 comprising selection components having two electrodes, e.g. diodes
• CPC Class Codes: H10N 70/20 Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/245 the species being metal cations, e.g. programmable metallization cells
• CPC Class Codes: H10N 70/881 Switching materials
• CPC Class Codes: H10N 70/8825 Selenides, e.g. GeSe
• CPC Class Codes: H10N 70/8833 Binary metal oxides, e.g. TaOx
• CPC Class Codes: H10N 70/8836 : Complex metal oxides, e.g. perovskites, spinels

Abstract

A switching element that includes a first semiconductor layer, the first semiconductor layer having a first portion and a second portion; a second semiconductor layer, the second semiconductor layer having a first portion and a second portion; an insulating layer disposed between the first semiconductor layer and the second semiconductor layer; a first metal contact in contact with the first portion of the first semiconductor layer forming a first junction and in contact with the first portion of the second semiconductor layer forming a second junction; a second metal contact in contact with the second portion of the first semiconductor layer forming a third junction and in contact with the second portion of the second semiconductor layer forming a fourth junction, wherein the first junction and the fourth junction are Schottky contacts, and the second junction and the third junction are ohmic contacts.

Claims

1. A method of forming a switching element comprising the steps of:

providing a layered article, the layered article comprising a first semiconductor layer, an insulating layer, and a second semiconductor layer;

forming a first mask region, wherein the first mask region protects only a first portion of the layered article;

doping only a second portion of the second semiconductor layer using a first energy level;

forming a second mask region, wherein the second mask region protects only a third portion of the layered article, wherein the first portion and the third portion of the layered article only partially overlap;

doping only a fourth portion of the first semiconductor layer using a second energy level, wherein the first energy level and the second energy level are different, thereby forming a doped layered article;

forming a contact mask on only a portion of the doped layered article;

etching a portion of at least the second semiconductor layer, the insulating layer, and the first semiconductor layer;

forming a first and a second metal contact in the etched regions of the second semiconductor layer, the insulating layer, and the first semiconductor layer.

2. The method according to claim 1, wherein the first energy is less than the second energy.

3. The method according to claim 1, wherein providing the layered article comprises:

providing a first layered structure, the first layered structure comprising a first substrate, a second insulating layer and the first semiconductor layer, wherein the second insulating layer is positioned between the first substrate and the first semiconductor layer;

providing a second layered structure, the second layered structure comprising the insulating layer and the second semiconductor layer;

placing the second layered structure in contact with the first layered structure so that the insulating layer of the second layered structure is adjacent the first semiconductor layer of the first layered structure and bonding the first layered structure to the second layered structure to form the layered article.

4. The method according to claim 3, wherein the second layered structure is formed at least in part by oxidizing a silicon wafer.

5. The method according to claim 3, wherein the second layered structure is formed at least in part by depositing an insulating material on a silicon wafer.

6. The method according to claim 1, wherein the first and second mask regions are configured to leave a portion of the layered article undoped.

7. The method according to claim 6, wherein the undoped portion of the layered article is substantially coincident with the portion of the doped layered article that is masked by the contact mask.

8. A method of forming a switching element comprising the steps of:

providing a layered article, the layered article comprising a first semiconductor layer, a second semiconductor layer and an insulating layer positioned between the first semiconductor layer and the second semiconductor layer;

doping only a portion of the second semiconductor layer using a first energy level;

doping only a portion of the first semiconductor layer using a second energy level, wherein the first energy level and the second energy level are different, thereby forming a doped layered article;

forming a contact mask on only a portion of the doped layered article;

etching a portion of at least the second semiconductor layer, the insulating layer, and the first semiconductor layer; and

forming a first and a second metal contact in the etched regions of the second semiconductor layer, the insulating layer, and the first semiconductor layer.

9. The method according to claim 8, wherein doping only a portion of the second semiconductor layer comprises the step of forming a first mask region, wherein the mask region comprises oxide materials, silicon nitrides, or photoresist.

10. The method according to claim 8, wherein doping only a portion of the first semiconductor layer comprises the step of forming a third mask region, wherein the mask region comprises oxide materials, silicon nitrides, or photoresist.

11. The method according to claim 8, wherein providing a layered article comprises:

providing a first layered structure, the first layered structure comprising a first substrate, a second insulating layer and the first semiconductor layer, wherein the second insulating layer is positioned between the first substrate and the first semiconductor layer;

providing a second layered structure, the second layered structure comprising the insulating layer and the second semiconductor layer;

placing the second layered structure in contact with the first layered structure so that the insulating layer of the second layered structure is adjacent the first semiconductor layer of the first layered structure and bonding the first layered structure to the second layered structure to form the layered article.

12. The method according to claim 11, wherein the second layered structure is formed at least in part by oxidizing a silicon wafer.

13. The method according to claim 11, wherein the second layered structure is formed at least in part by depositing an insulating material on a silicon wafer.

14. The method according to claim 11, wherein the first and second mask regions are configured to leave a portion of the layered article undoped.

15. The method according to claim 11, wherein the undoped portion of the layered article is substantially coincident with the portion of the doped layered article that is masked by the contact mask.

16. The method according to claim 8, wherein the first energy is less than the second energy.

17. A method of forming a switching element comprising the steps of:

providing a first layered structure, the first layered structure comprising a first substrate, a second insulating layer and the first semiconductor layer, wherein the second insulating layer is positioned between the first substrate and the first semiconductor layer;

providing a second layered structure, the second layered structure comprising the insulating layer and the second semiconductor layer;

placing the second layered structure in contact with the first layered structure so that the insulating layer of the second layered structure is adjacent the first semiconductor layer of the first layered structure and bonding the first layered structure to the second layered structure to form a layered article;

forming a first mask region, wherein the first mask region protects only a first portion of the layered article;

doping only a second portion of the second semiconductor layer using a first energy level;

forming a second mask region, wherein the second mask region protects only a third portion of the layered article, wherein the first portion and the third portion of the layered article only partially overlap;

doping only a fourth portion of the first semiconductor layer using a second energy level, wherein the first energy level and the second energy level are different, thereby forming a doped layered article;

forming a contact mask on only a portion of the doped layered article;

etching a portion of at least the second semiconductor layer, the insulating layer, and the first semiconductor layer;

forming a first and a second metal contact in the etched regions of the second semiconductor layer, the insulating layer, and the first semiconductor layer.

18. The method according to claim 17, wherein the first energy is less than the second energy.

19. The method according to claim 17, wherein the first and second mask regions are configured to leave a portion of the layered article undoped.

20. The method according to claim 17, wherein the undoped portion of the layered article is substantially coincident with the portion of the doped layered article that is masked by the contact mask.