High aspect ratio trench structures with void-free fill material

• US 8,198,196 B1
• Filed: 06/06/2011
• Issued: 06/12/2012
• Est. Priority Date: 01/15/2008
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Murphy, James J., Chen, Hui, Valdez, Eileen
• Primary Examiner(s): HA, NATHAN W
• Application Number:
  US13/154,228
• Publication Number:
  US 20120142155A1
• Time in Patent Office: 372 Days
• Field of Search: 438/270, 438/275, 438/272, 257330-334, 257/E29.262
• US Class Current: 438/720
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4925 with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with only a vertical doping structure or vertical doping variation H01L29/4916
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/495 the conductor material next to the insulator being a simple metal, e.g. W, Mo H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4975 being a silicide layer, e.g. TiSi2
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A field effect transistor (FET) includes a trench extending into a semiconductor region. A conductive electrode is disposed in the trench, and the conductive electrode is insulated from the semiconductor region by a dielectric layer. The conductive electrode includes a conductive liner lining the dielectric layer along opposite sidewalls of the trench. The conductive liner has tapered edges such that a thickness of the conductive liner gradually increases from a top surface of the conductive electrode to a point in lower half of the conductive electrode. The conductive electrode further includes a conductive fill material sandwiched by the conductive liner. The FET further includes a drift region of a first conductivity type in the semiconductor region, and a body region of a second conductivity type extending over the drift region. Source regions of the first conductivity type extend in the body region adjacent the trench.

Claims

1. A method of forming a trench gate field effect transistor, comprising:

forming a trench in a semiconductor region;

forming a conductive electrode in the trench, the conductive electrode being insulated from the semiconductor region by a dielectric layer, the step of forming a conductive electrode comprising;

forming a conductive liner lining the dielectric layer along opposite sidewalls of the trench, the conductive liner having tapered edges such that a thickness of the conductive liner gradually increases from a top surface of the conductive electrode to a point in lower half of the conductive electrode, and

forming a conductive fill material in an opening formed by the conductive liner;

forming a body region of a first conductivity type in the semiconductor region; and

forming source regions of the first conductivity type in the body region.

2. The method of claim 1 wherein both the conductive liner and the conductive fill material comprise polysilicon.

3. The method of claim 1 wherein the conductive liner comprises polysilicon and the conductive fill material comprises metal-containing material.

4. The method of claim 1 wherein the conductive electrode is a gate electrode and the dielectric layer is a gate dielectric layer.

5. The method of claim 4 further comprising:

before forming the gate electrode, forming a thick bottom dielectric extending along the bottom of the trench.

6. The method of claim 1 wherein the conductive liner is discontinuous along a bottom of the conductive electrode so that the conductive liner comprises discrete conductive spacers extending over the dielectric layer along opposite sidewalls of the trench.

7. The method of claim 1 wherein the conductive liner extending along opposite sidewalls of the trench is continuous along a bottom of the conductive electrode.

8. The method of claim 1 wherein the conductive electrode is a shield electrode disposed in a lower portion of the trench, and the dielectric layer is a shield dielectric layer lining lower trench sidewalls.

9. The method of claim 8 further comprising:

forming a gate dielectric layer lining upper trench sidewalls, the shield dielectric layer being thicker than the gate dielectric layer; and

forming a gate electrode disposed in the trench over the shield electrode, the gate and shield electrode being insulated from one another by an inter-electrode dielectric layer.

10. The method of claim 9 wherein the step of forming a gate electrode comprises:

forming a conductive liner lining the gate dielectric layer, the conductive liner of the gate electrode having tapered edges such that a thickness of the conductive liner of the gate electrode gradually increases from a top surface of the gate electrode to a point in lower half of the gate electrode, and

forming a conductive fill material filling an opening formed by the conductive liner of the gate electrode.

11. The method of claim 1 where in the conductive liner is formed using a bevel etch process.

12. The method of claim 1 wherein the conductive liner is formed using an anisotropic etch process.