Power core for use in circuitized substrate and method of making same

• US 8,198,551 B2
• Filed: 05/18/2010
• Issued: 06/12/2012
• Est. Priority Date: 05/18/2010
• Status: Active Grant

• Current Assignee: TTM Technologies North America, LLC (TTM Technologies Incorporated)
• Original Assignee: Endicott Interconnect Technologies Incorporated
• Inventors: Japp, Robert M., Papathomas, Kostas, Antesberger, Timothy, Kresge, John Steven
• Primary Examiner(s): Nguyen, Hoa C
• Application Number:
  US12/782,187
• Publication Number:
  US 20110284273A1
• Time in Patent Office: 756 Days
• Field of Search: 174260-266
• US Class Current: 174/262
• CPC Class Codes: H05K 2201/068 wherein the coefficient of thermal expansion is important
• CPC Class Codes: H05K 3/4617 characterized by laminating only or mainly similar single-sided circuit boards
• CPC Class Codes: H05K 3/4641 having integrally laminated metal sheets or special power cores
• CPC Class Codes: Y10T 29/49117 Conductor or circuit manufacturing

Abstract

A power core adapted for use as part of a circuitized substrate, e.g., a PCB or LCC. The core includes a first layer of low expansion dielectric and two added layers of a different low expansion dielectric bonded thereto, with two conductive layers positioned on the two added low expansion dielectric layers. At least one of the conductive layers serves as a power plane for the power core, which in turn is usable within a circuitized substrate, also provided. Methods of making the power core and circuitized substrate are also provided. The use of different low expansion dielectric materials for the power core enables the use of support enhancing fiberglass in one layer while such use is precluded in the other two dielectric layers, thus preventing CAF shorting problems in highly precisely defined thru holes formed within the power core.

Claims

1. A power core for use in circuitized substrates, said power core comprising:

a first layer of a first low expansion dielectric material including first and second opposing sides and at least one opening extending there-through;

second and third layers of a second low expansion dielectric material different from said first low expansion dielectric material and positioned on said first and said second opposing sides of said first layer of low expansion dielectric material, respectively, and within said at least one opening;

first and second conductive layers positioned on said second and said third layers of said low expansion dielectric material, respectively, and not within said at least one opening; and

at least one thru hole positioned within said at least one opening and extending substantially from said first conductive layer to said second conductive layer.

2. The power core of claim 1 wherein said first low expansion dielectric material comprises thermosetting resin, fiberglass and a quantity of inorganic particulates.

3. The power core of claim 2 wherein said inorganic particulates each has a size within the range of about 0.10 mils to about 1.4 mils.

4. The power core of claim 3 wherein said inorganic particulates comprise silica, said silica occupying from about 3 to about 49 percent by weight of said thermosetting resin and said fiberglass cloth constitutes from about 35 to about 55 percent by weight of the resin.

5. The power core of claim 1 wherein said second low expansion dielectric material different from said first low expansion dielectric material comprises thermosetting resin and a quantity of inorganic particulates, said second low expansion dielectric material not including fiberglass cloth or the like therein.

6. The power core of claim 5 wherein said inorganic particulates of said second low expansion dielectric material each has a size within the range of about 0.10 mils to about 1.00 mil.

7. The power core of claim 6 wherein said inorganic particulates of said second low expansion dielectric material comprise silica constituting from about 30 to about 75 percent by weight of said thermosetting resin.

8. The power core of claim 1 wherein each of said first and said second conductive layers comprise copper or copper alloy material and are positioned on said second and third layers of said low expansion dielectric material, respectively, and not within said at least one opening.

9. The power core of claim 1 wherein said at least one thru hole positioned within said at least one opening includes at least one layer of copper or copper alloy material.

10. A circuitized substrate comprising:

a power core including a first layer of a first low expansion dielectric material including first and second opposing sides and at least one opening extending there-through;

second and third layers of a second, different low expansion dielectric material from said first low expansion dielectric material and positioned on said first and said second opposing sides of said first layer of low expansion dielectric material, respectively, and within said at least one opening, first and second conductive layers positioned on said second and third layers of said low expansion dielectric material, respectively, and not within said at least one opening, and at least one thru hole positioned within said at least one opening and electrically isolated from said first and said second conductive layers; and

a plurality of alternating layers of dielectric material and conductive material on at least one side of said power core and bonded thereto, selected ones of said layers of conductive material adapted for carrying electrical signals.

11. The circuitized substrate of claim 10 wherein said first low expansion dielectric material comprises thermosetting resin, fiberglass and a quantity of inorganic particulates.

12. The circuitized substrate of claim 11 wherein said inorganic particulates each has a size within the range of about 0.10 mils to about 1.4 mils.

13. The circuitized substrate of claim 11 wherein said inorganic particulates comprise silica constituting from about 3 to about 49 percent by weight of said thermosetting resin, and said fiberglass cloth constituting from about 35 to about 55 percent by weight of the resin.

14. The circuitized substrate of claim 10 wherein said second low expansion dielectric material different from said first low expansion dielectric material comprises thermosetting resin and a quantity of inorganic particulates, said second low expansion dielectric material not including fiberglass cloth or the like therein.

15. The circuitized substrate of claim 14 wherein said inorganic particulates of said second low expansion dielectric material each has a size within the range of about 0.10 mils to about 1.00 mil.

16. The circuitized substrate of claim 15 wherein said inorganic particulates of said second low expansion dielectric material comprise silica constituting from about 30 to about 75 percent by weight of said thermosetting resin.

17. The circuitized substrate of claim 10 wherein each of said first and said second conductive layers comprise copper or copper alloy material, and are positioned on said second and said third layers of said low expansion dielectric material, respectively, and not within said at least one opening.

18. The circuitized substrate of claim 10 wherein said at least one thru hole positioned within said at least one opening includes at least one layer of copper or copper alloy material.

19. The circuitized substrate of claim 10 wherein said alternating layers of dielectric material and conductive material comprise epoxy resin and copper or copper alloy, respectively.

20. A method of making a power core for use in a circuitized substrate, the method comprising:

providing a first layer of a first low expansion dielectric material including first and second opposing sides;

forming at least one opening extending through said first layer of said first low expansion dielectric material from said first opposing side to said second opposing side;

positioning second and third layers of a second low expansion dielectric material different from said first low expansion dielectric material on said first and said second opposing sides of said first layer of low expansion dielectric material, respectively;

bonding said second and said third layers of said second low expansion dielectric material different from said first low expansion dielectric material to said first layer of said first low expansion dielectric material such that at least some of said second low expansion dielectric material of both of said second and said third layers extends within and substantially fills said at least one opening;

forming first and second conductive layers on said second and said third layers of said low expansion dielectric material, respectively, and not within said at least one opening; and

forming at least one thru hole within said at least one opening having said second low expansion dielectric material of both of said second and said third layers therein.

21. The method of claim 20 wherein said forming of said at least one opening extending through said first layer of said first low expansion dielectric material from said first opposing side to said second opposing side is accomplished using at least one of the group:

a laser, and a mechanical drill.

22. The method of claim 20 wherein said bonding said second and said third layers of said second low expansion dielectric material different from said first low expansion dielectric material to said first layer of said first low expansion dielectric material such that at least some of said second low expansion dielectric material of both said second and said third layers extends within and substantially fills said at least one opening is accomplished using lamination.

23. The method of claim 22 wherein said lamination is accomplished at temperatures of from about 180 degrees C. to about 230 degrees C. and at pressures within the range of about 200 PSI to 1000 PSI.

24. The method of claim 20 wherein said forming of said first and said second conductive layers on said second and third layers of said low expansion dielectric material, respectively, is accomplished prior to said bonding of said second and said third layers of said second low expansion dielectric material different from said first low expansion dielectric material to said first layer of said first low expansion dielectric material.

25. The method of claim 24 wherein said first and second conductive layers are formed on said second and third layers of said low expansion dielectric material, respectively, by coating.

26. The method of claim 20 wherein said forming of said at least one thru hole within said at least one opening within said first layer of said first low expansion dielectric material having said second low expansion dielectric material of both of said second and said third layers therein is accomplished by forming at least one opening within said second low expansion dielectric material of both of said second and said third layers within said at least one opening within said first layer of said first low expansion dielectric material and then forming a layer of conductive material on said at least one opening within said second low expansion dielectric material of both of said second and said third layers within said at least one opening within said first layer of said first low expansion dielectric material.

27. The method of claim 26 wherein said forming of said at least one opening within said second low expansion dielectric material of both said second and said third layers within said at least one opening within said first layer of said first low expansion dielectric material is accomplished using a laser.

28. The method of claim 27 wherein said forming said layer of conductive material on said at least one opening within said second low expansion dielectric material of both said second and said third layers within said at least one opening within said first layer of said first low expansion dielectric material is accomplished using electroplating.

29. The method of claim 20 further including bonding a plurality of alternating layers of dielectric material and conductive material on at least one side of said power core to form a circuitized substrate.