High reflectance terahertz mirror and related method

• US 8,198,590 B2
• Filed: 10/30/2008
• Issued: 06/12/2012
• Est. Priority Date: 10/30/2008
• Status: Expired due to Fees

• Current Assignee: Honeywell International Inc.
• Original Assignee: Honeywell International Inc.
• Inventors: Cox, James Allen, Higashi, Robert
• Primary Examiner(s): Porta, David
• Assistant Examiner(s): Boosalis, Faye
• Application Number:
  US12/261,911
• Publication Number:
  US 20100108891A1
• Time in Patent Office: 1,321 Days
• Field of Search: 250/341.8, 250/208.1, 250/370.01, 257/E21.002, 257/E21.032, 438/458, 438/68
• US Class Current: 250/341.8
• CPC Class Codes: G01N 21/3504 for analysing gases, e.g. multi-gas analysis
• CPC Class Codes: G01N 21/3581 using far infrared light; using Terahertz radiation
• CPC Class Codes: G02B 5/0816 Multilayer mirrors, i.e. having two or more reflecting layers G02B5/0883, G02B5/0891 take precedence
• CPC Class Codes: H01S 3/08059 Constructional details of the reflector, e.g. shape mirrors in general G02B5/08; mountings for mirrors G02B7/18

Abstract

A method includes forming a plurality of mirror periods, stacking the mirror periods, and bonding the mirror periods together to form a high reflectance mirror. At least one of the mirror periods is formed by bonding a first semiconductor layer to a first side of a film layer (where the film layer is formed on a second semiconductor layer), forming an opening through the second semiconductor layer to expose the film layer, and cutting through the first semiconductor layer, the film layer, and the second semiconductor layer. The first semiconductor layer could include a high resistivity silicon wafer, the film layer could include an oxide film, and the second semiconductor layer could include a silicon wafer. The high resistivity silicon wafer could be approximately 110 μm thick, and the silicon wafer could be approximately 125 μm thick. The opening through the second semiconductor layer could be 1.25 cm to 1.75 cm in width.

Claims

1. A method comprising:

forming a plurality of mirror periods, wherein at least one of the mirror periods is formed by;

bonding a first semiconductor layer to a first side of a film layer, a second semiconductor layer bonded to a second side of the film layer opposite the first side;

forming an opening through the second semiconductor layer to expose the film layer and form a notch in the second semiconductor layer, wherein remaining portions of the second semiconductor layer form sidewalls of the notch; and

cutting through the first semiconductor layer, the film layer, and the second semiconductor layer;

stacking the mirror periods; and

bonding the mirror periods together to form a high reflectance mirror, the notch in the at least one mirror period forming a cavity when the mirror periods are bonded together.

2. The method of claim 1, wherein at least one of the mirror periods is formed further by:

depositing a photoresist layer over the first semiconductor layer, the photoresist layer including two vias; and

etching the first semiconductor layer through the vias to form street patterns in the first semiconductor layer.

3. The method of claim 2, wherein cutting through the first semiconductor layer, the film layer, and the second semiconductor layer comprises cutting along the street patterns in the first semiconductor layer.

4. The method of claim 1, wherein forming the opening through the second semiconductor layer comprises:

depositing a photoresist layer over the second semiconductor layer, the photoresist layer including a first open area; and

etching the second semiconductor layer through the first open area to form the opening.

5. The method of claim 4, wherein:

the photoresist layer further includes a second open area;

etching the second semiconductor layer and cutting through the first semiconductor layer, the film layer, and the second semiconductor layer form a glue notch; and

bonding the plurality of mirror periods together comprises depositing a bonding material along the glue notches of the mirror periods.

6. The method of claim 1, wherein:

the first semiconductor layer comprises a high resistivity silicon wafer;

the film layer comprises an oxide film; and

the second semiconductor layer comprises a silicon wafer.

7. The method of claim 6, wherein:

the high resistivity silicon wafer is approximately 110 μ

m thick; and

the silicon wafer is approximately 125 μ

m thick.

8. The method of claim 1, wherein the opening through the second semiconductor layer is 1.25 cm to 1.75 cm in width.

9. The method of claim 1, further comprising:

a spacer layer formed under a bottom one of the stacked mirror periods.

10. The method of claim 1, wherein forming the opening through the second semiconductor layer comprises performing a deep reactive ion etch.

11. The method of claim 1, wherein forming the opening through the second semiconductor layer exposes the film layer without etching through the film layer.

12. The method claim 1, wherein:

cutting through the first semiconductor layer, the film layer, and the second semiconductor layer comprises cutting through the first semiconductor layer, the film layer, and the second semiconductor layer in a first direction; and

forming the opening through the second semiconductor layer comprises etching through the second semiconductor layer in a second direction opposite the first direction.

13. The method of claim 1, further comprising:

forming a weep hole though the second semiconductor layer; and

using the weep hole to achieve pressure equilibration between adjacent mirror periods when the mirror periods are bonded together.

14. An apparatus comprising:

a plurality of mirror periods stacked and bonded together, each mirror period comprising;

a first semiconductor layer bonded to a first side of a film layer; and

a second semiconductor layer bonded to a second side of the film layer opposite the first side, the second semiconductor layer comprising an opening that exposes the film layer and forms a notch in the second semiconductor layer, wherein remaining portions of the second semiconductor layer form sidewalls of the notch;

wherein the notches in at least some of the stacked mirror periods form cavities.

15. The apparatus of claim 14, wherein the first semiconductor layer in each mirror period has a high refractive index and material in the cavity of each mirror period has a low refractive index, giving the apparatus a high-index|low-index mirror period.

16. The apparatus of claim 14, wherein:

each mirror period further comprises a glue notch along its side; and

the mirror periods are bonded together by a bonding material deposited along the glue notches of the mirror periods.

17. The apparatus of claim 14, wherein:

the first semiconductor layer in each mirror period comprises a high resistivity silicon wafer;

the film layer in each mirror period comprises an oxide film; and

the second semiconductor layer in each mirror period comprises a silicon wafer.

18. The apparatus of claim 17, wherein:

the high resistivity silicon wafer in each mirror period is approximately 110 μ

m thick; and

the silicon wafer in each mirror period is approximately 125 μ

m thick.

19. The apparatus of claim 14, wherein the opening through the second semiconductor layer in each mirror period is 1.25 cm to 1.75 cm in width.

20. The apparatus of claim 14, further comprising:

a spacer layer under a bottom one of the stacked mirror periods.

21. The apparatus of claim 14, wherein the cavity in each mirror period comprises air.

22. A method comprising:

forming a semiconductor structure by fusion bonding a first wafer layer to a first side of an oxide film, a second wafer layer bonded to a second side of the oxide film opposite the first side;

forming an aperture through the second wafer layer to expose the oxide film and form a notch in the second wafer layer, wherein remaining portions of the second wafer layer form sidewalls of the notch;

dicing the semiconductor structure; and

stack bonding a plurality of the diced semiconductor structures to form a high reflectance mirror, the notch in at least one diced semiconductor structure forming a cavity when the diced semiconductor structures are stack bonded.

23. The method of claim 22, wherein the first wafer layer comprises a high resistivity silicon wafer.